Say I have 3 modules:
Do you have registers on the boundaries of your partitions? If you don't, then paths in the top level may become critical. Remember that there is no optimization across partition boundaries, so combinational logic on the boundaries of the design partitions cannot be optimized with respect to the top level.
Adding registers at the boundaries can fix this, allowing you to run the design faster at the expense of an extra cycle of latency.
Is the failing path within the sub-modules? Have you tried to preserve timing-closed partitions and use in the top design?
What is your interconnect usage? Designs with an average value below 50% typically do not have any problems with routing. Designs with an average between 50-65% may have difficulty routing. Designs with an average over 65% typically have difficulty meeting timing unless the RTL tolerates a highly utilized chip. Peak values at or above 90% are likely to have problems with timing closure; a 100% peak value indicates that all routing in an area of the device has been used, so there is a high possibility of degradation in timing performance.
find the interconnect usage as below:
Average interconnect usage (total/H/V) 50.7% / 48.7% / 57.0%
Peak interconnect usage (total/H/V) 80.4% / 81.7% / 86.1%
I think the screenshot you shared is for quartus pro edition. I am using intel quartus standard edition 18.1
I find only routing usage summary under logic and routing section ,which only talks about resources like Block interconnects
and not about module level usage . Is there someother option to check the same w.r.t each module of my project?
The report in the Pro edition is different from the Standard edition. In this case, you have to check the routing utilization in the Chip Planner.
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