Is there some place on the Internet I could go to read about what Intel Quartus Prime Lite actually does, or what it is for? If not, can anyone on this forum tell me what it does or what it is for?
Intel Quartus Prime is a fully integrated design tool that you can use it to develop an FPGA design from initial design to device programming. Intel Quartus Prime Lite edition can be downloaded and used without a license but it has limited device support and features. You can watch the video overview of Intel Quartus Prime design software at the link here: Intel Quartus Prime Software Overview
For further details, you can continue down the page to check on Quick Links to Intel® Quartus® Prime Design Software Brochure and the training resources to learn more about the design tool.
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Right now I use Icarus to simulate my Verilog. Could I use Quartus to do that too? I'm wondering if I should switch from Icarus to Quartus. I'd have to use Quartus Lite, because I don't have money to get the complete Quartus.
First, I use Icarus Verilog for my simulation environment for Altera FPGA/CPLD designs. And use GTKwave as the waveform viewer. I found it to be an excellent environment.
Altera/Intel Quartus does not do any simulation per se. To handle simulation they supply a version of ModelSim as the simulator. See: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html for more information. There is a free version you can download.
I've personally never found the need to use it, as I am strictly verilog based. The ModelSim simulator can handle both verilog and vhdl if that is a requirement for you. Also has it's own waveform viewer.
Ak6dn: "First, I use Icarus Verilog for my simulation environment for Altera FPGA/CPLD designs." Okay; sounds like I'm best off just sticking with Icarus for now.
"I've personally never found the need to use it, as I am strictly verilog based." Do you know a good place to go for questions about Verilog? I've got two in particular that I'm trying to get answered, but I'm having trouble finding a forum where I can get the matter resolved.
Verilog forums. Not an easy answer. You can ask here, but it sometimes might take a while.
Also look here: https://groups.google.com/g/comp.arch.fpga
It's pretty active and you might get an answer quicker.