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What is: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.tr file and how to use it?

ThomasTessier
New Contributor I
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I am running an ArriaV design in simulation (QuartusPrime 21.1 with Cadence Xcelium). An in my simulation directory I get the following file: 

altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.tr

I am wondering what is generating the file, how do you use it and lastly can you disable it?

My Platform Designer consists of DDR3 memory controller, JTAG Master/Avalon BFM Master, and SPI port.  There is other pieces but for this discussion these are the Altera pieces that might be responsible for dropping this file.

Thanks in advance,

TomT...

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AdzimZM_Intel
Employee
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Hi Tom,


I can see which file that you are mentioning and it's a file that has been generated when running the simulation. This file actually captures the transaction of the simulation. So the size is depends on the transaction.

If you want to disable this file, you can check in the testbench file located in the submodules folder.

The name of the testbench file is altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v.

In the testbench file, you can scroll down until line 694 to 704. These lines will create the file and write the transactions into the file.

By disabling lines 694 to 704, the file will not generated.


Regards,

Adzim


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AdzimZM_Intel
Employee
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Hi Tom,


I believe the file that you mention was a file from sequencer module.

The sequencer module will run the calibration process for the memory interface.

Usually this module is not expose to user logic and not able to disable it.


Regards,

Adzim


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ThomasTessier
New Contributor I
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AdzimZM,

 

Not being able to disable it is not really acceptable.  For my simulation this file is 19MBytes and I haven't even use the DDR3 at this point.  In fact my simulation doesn't have a DDR3 simulation model attached to the FPGA design. I was actually planning on replacing the DDR3 Avalon device with the Avalon BFM Slave for simulation so I would have some data to playback.

So is there really no way to disable the creation of this file, I would have expected a Parameter or at a minimum a `define that could do the work?

TomT... 

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AdzimZM_Intel
Employee
772 Views

Hi Tom,


I can see which file that you are mentioning and it's a file that has been generated when running the simulation. This file actually captures the transaction of the simulation. So the size is depends on the transaction.

If you want to disable this file, you can check in the testbench file located in the submodules folder.

The name of the testbench file is altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v.

In the testbench file, you can scroll down until line 694 to 704. These lines will create the file and write the transactions into the file.

By disabling lines 694 to 704, the file will not generated.


Regards,

Adzim


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ThomasTessier
New Contributor I
714 Views

So the solution is to comment out some code in my INSTALL directory?  I will accept that solution but a better one would be if you provided a switch I can set to disable this behavior if I want.  Your assumption is that my INSTALL directory is NOT on a shared system of many users (that is my case) and I could just make this change.  Which I cannot!

Thanks,

TomT...

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AdzimZM_Intel
Employee
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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