When I do simulation in Modelsim, in sim tab, there are "Assertion misses" and "Assertion hits", I attached a screenshot to show it, what is the mean of this?Thanks in advance.
In VHDL, an assertion hit is an assert statement that did not fail. A miss is an assert statement that failed at least once. The words pass and fail are not used because in other languages, it possible to have the assertion pass, but still not considered a hit. (a vacuous pass) And an assertion that does not ever execute can be a miss.
Thanks very much, dave_59.Actually, I am not clear what the assert statement it is. Is the assert statement like an assertion of reset? Could you please take an example to briefly describe what assert statement is? Thanks so much.