Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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What's Internal and External I/O PLLs in Arria10 I/O Banks ??


Can i get some clarification on what is internal /external PLL in the I/O banks?????

As per my view both meant to be the same . But while using LVDS Serdes IP, In default, IO PLL(Internal) will be given to LVDS Serdes.

So Input clock will be given to this PLL and it will drive the LVDS Serdes.

And If I use two LVDS I/O Serdes channels as Receivers in arria10, Both LVDS channels will use the same I/O PLL(internal) or we need to provide separate I/O PLLs for each channels externally??


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