Using Quartus II v8.0 with EP3SL50F484. I have an 8bit output bus in my project that is assigned to LVDS. When I use the pin planner to drag the signal to the positive pin of a diff tx pair, the planner arbitrarily assigns an unrelated signal to the negative pin of the pair.
I am really sorry to inform you that, I do not have access to Quartus 8.0 to check from myside and dont have the data base also .
As per me if possible can you try to manually assign the pin in Qsf file.