Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14961 Discussions

When I use the pin planner to drag the signal to the positive pin of a diff tx pair, the planner arbitrarily assigns an unrelated signal to the negative pin of the pair.

MPogo1
Beginner
257 Views

Using Quartus II v8.0 with EP3SL50F484. I have an 8bit output bus in my project that is assigned to LVDS. When I use the pin planner to drag the signal to the positive pin of a diff tx pair, the planner arbitrarily assigns an unrelated signal to the negative pin of the pair.

0 Kudos
1 Reply
Rahul_S_Intel1
Employee
67 Views

Hi ,

I am really sorry to inform you that, I do not have access to Quartus 8.0 to check from myside and dont have the data base also .

As per me if possible can you try to manually assign the pin in Qsf file.

Reply