When I turn on smart compilation and then change a parameter in the design(just a constant value stored in a register or a constant connected to combinational logic of fixed length like and adder or a >), the new design does not function properly. If I turn off smart compilation and do a full compilation with the same parameters, the design functions. Does smart compilation not guarantee the functionality of the design?
Also, before asking qu estions about the design and debugging it, would it not be possible to start by answering the question of whether smart compilation guarantees functionality to begin with?
In case it is supposed to guarantee functionality, then the following information may be important:
The parameters I am changing are all declared in a .vh file which is included in all my verilog files. While the .vh file is in the project directory, it is not included in the project. Could it be that Quartus then interprets all files in the project as untouched since the last compilation and therefore skips all of them in the compilation, effectively ignoring the changes in the included .vh file?
I am using Quartus Prime 18.1 standard edition. I did not simulate the design after each of the compilations. I already had the expected results so I just loaded the design on the FPGA and compared. After a change of the parameters and a a smart compile the FPGA results deviated from the expected results, while doing a full compile after changing the parameters produced FPGA results that matched the expected results.
This could be a bug in using the smart compilation. Can you help to share a simplified design that could duplicate this issue - causing design does not function properly after smart compilation? I will consult with the engineering team regarding this.
As you mentioned previously, please turn off the smart compilation and instead do a full compilation for the current design. I apologize for the inconvenience caused.
I am too busy to try to replicate the issue in a minimal example. All the information I can give at the moment is that the parameters are in a .vh file that is included in the project, and included in all the verilog modules. If I change a parameter in that file and smart compile the compilation only takes 2 seconds and produces no compilation report. I haven't confrmed this, but from the behaviour after a smart compilation I suspect that the parameter change is ignored completely so the design runs with the old parameters unless I do a full compilation. Maybe smart compilation doesn't account for changes in .vh files.
I am not able to duplicate the issue. Understand that you are occupied but it would best if you could share with us a simplified design. Perhaps you can share the details on the .vh files that you mentioned and what are the parameters changes.