In Qsys I specify the "Memory clock frequency" as 500MHz. After compilation I run the timing analyzer, when I run "Report Clocks" it shows:
When I run "Report Fmax Summary" it shows:
It "passes" timing with Fmax of 218MHz. This is insufficient when mem_ck is really 500MHz and afi_clk is half that rate at 250MHz. I scoped mem_ck on our board and confirmed it being 500MHz which is what I specified in QSYS.
What is the cause for this discrepancy in the timequest analyzer?
Quartus Prime Standard 17.1 and 18.1
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I can see you are using Half rate on Avalon-MM interface. For half rate, the maximum supported frequency for DDR3 is 400 MHz which means 500MHz is not supported for this type of interface. That's the reason you see below setting after compilation.
For more details, you can refer to this EMIF spec: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/exter...
I am truly sorry for the inconvenience caused.
Thank you for your response, I have overlooked that the max rate is 400MHz. Unfortunately, when I enter 400MHz into Quartus the Timequest Analyzer still exhibits the same behavior of showing the clock summary at 80% of the 400MHz.
This would still cause issues as the .sdc is specifying the AFI_CLK at a lower frequency so the logic is not being optimized to run at the correct frequency. What is causing this discrepancy?
May I know what is the speed grade of the device used? It would be better if you can share with me the full part number of the device 😊
Also, is there other clock source used beside afi_clk? The reason I ask this because using another clock would cause Qsys to automatically instantiate clock-crossing logic, potentially degrading performance.