Why can't I load my simple design into my board? Quartus II programmer not working

[Altera_Forum]

Hello guys, I'm learning the basics of FPGA, my board is the Altera DE1-SOC and Quartus II Prime. I created a simple NOR gate with input 2 buttons (KEY0,KEY1) and output a Led (LEDR0), I opened the programmer but (according to the manual I'm following) should inmediatly load my .sof file, but it doesn't, then I tried to located by myself and start it but it says "FAILED" and refuse to load into the FPGA. 

   http://www.alteraforum.com/forum/attachment.php?attachmentid=12607&stc=1    I however, click on "autodetect" and it firstly detect the factory design which is something like a counter, then I deleted on of the two modules and load my design and it works.   http://www.alteraforum.com/forum/attachment.php?attachmentid=12608&stc=1   in both combinations. I don't understand what's happening. Could you please help me to clarify this, do I have to do this every time I'm intending to load a design into the board?  http://www.alteraforum.com/forum/attachment.php?attachmentid=12609&stc=1

[Altera_Forum]

The .sof file does not load automatically. If you browse for it and save the programming page, the next time it will automatically load. If you change your design & synthesize it again, it also automatically loads the new generated sof file. 

 As I see, there are two parts (Either 2 FPGAs or An FPGA & A Flash) on the board. You can use auto-detect feature to list parts in the JTAG chain. Then you should select your specific part (the FPGA you target) & load the sof file. There may be multiple FPGAs on the board, so this may be necessary.

[Altera_Forum]

The SOC chips usually put up a dialog asking you what chip you have. Did you see this?

[Altera_Forum]

--- Quote Start ---  The SOC chips usually put up a dialog asking you what chip you have. Did you see this?  --- Quote End ---    Do you mean the setting screens of the project? I do that everytime I start a project, on which I select my DE1-SOC specific chip.    --- Quote Start ---  The .sof file does not load automatically. If you browse for it and save the programming page, the next time it will automatically load. If you change your design & synthesize it again, it also automatically loads the new generated sof file.   As I see, there are two parts (Either 2 FPGAs or An FPGA & A Flash) on the board. You can use auto-detect feature to list parts in the JTAG chain. Then you should select your specific part (the FPGA you target) & load the sof file. There may be multiple FPGAs on the board, so this may be necessary.  --- Quote End ---    As far as I know, this is just a basic FPGA University program, it has only one FPGA, in the uploaded image appears 2 FPGAs, but that's only me trying to load my design after clicking in the "auto detect" button. The other component is an HPS I think.  I'm also facing the issue that everytime I open the programmer, it seemingly opening a new "file" of some kind named "chain", at the moment I have chain20.cdf, the numbers of times I have opened the programmer, wherever I think I should just edit the first "chain". Please guys help me to clarify the correct method to do this.  https://www.youtube.com/watch?v=if4iiz4i8vk  following this video, I fail to do as him. First his programmer recognize inmediatly the design, secondly when he delete the file and load it again, at clicking start, it sucessfully load the design in the chip, to me it says "FAILED"

[Altera_Forum]

I am following now the Manual of the device. It seems auto-detecting is the way to program the device, then delete or click in the 5SCSEMA5F31 device and change it with my design, I understand this now. Although, what I still confuse me is that you can also delete HPS device and load my design files thus having the third picture, with seemingly 2 FPGAS, which is not.  

 Is this a flaw from the system correct?

[Altera_Forum]

Two items are autodetected. The HPS used for debugging HPS software. The FPGA is used for programming the FPGA, using the NIOS debugger, etc.  

 When the autodetect finishes, don't delete the HPS. Select the FPGA side and set for programming as instructed in the documentation.

[Altera_Forum]

--- Quote Start ---  Two items are autodetected. The HPS used for debugging HPS software. The FPGA is used for programming the FPGA, using the NIOS debugger, etc.   When the autodetect finishes, don't delete the HPS. Select the FPGA side and set for programming as instructed in the documentation.  --- Quote End ---    Thanks Galfonz, then how would explain the third picture, where I did delete the HPS and added my FPGA design, showing up 2 FPGAs and it still works? This is the root of my confusion.

[Altera_Forum]

It set one FPGA instance into bypass mode. This was likely the HPS. The FPGA then showed up and could be programmed.