Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
16004 Discussions

Why do I get this Synthesis error?

John
Novice
1,355 Views

I am building a variant of a working project, using Quartus Prime Lite.

It fails Analysis & Synthesis right at the end (97%).

I have tried in V17.1.0 and 18.1, same error with both.

It occurred after I modified an Avalon FIFO memory component in my qsys system.

When I compare the sdc file from this project with my earlier successful project, only the project names (my_proj) are different.

Any Ideas/workarounds?

Thanks John.

 

Info (332104): Reading SDC File: 'd:/sandbox/wh/db/ip/my_proj/submodules/my_proj_fifo_0.sdc'

Error (332000): ERROR: You must open a project before you can use this command.

 

  while executing

"get_names -entity $search_entity -filter * -node_type hierarchy"

  (procedure "altera_private_get_entity_instances::find_instances_of_entit..." line 14)

  invoked from within

"altera_private_get_entity_instances::find_instances_of_entity $entity_name $nowarn"

  (procedure "get_entity_instances_internal" line 72)

  invoked from within

"get_entity_instances_internal 0 my_proj_fifo_0"

  invoked from within

"get_entity_instances $entity_name"

  (procedure "apply_sdc_pre_dcfifo" line 3)

  invoked from within

"apply_sdc_pre_dcfifo my_proj_fifo_0"

  (file "d:/sandbox/wh/db/ip/my_proj/submodules/my_proj_fifo_0.sdc" line 82)

 

0 Kudos
1 Solution
Abe
Valued Contributor II
404 Views

Does your project use any DCFIFO IP blocks, If so delete the component, create a new instance and try building it again.

View solution in original post

4 Replies
JOHI
New Contributor II
404 Views

Hello,

 

Sometimes you need to clean your project + delete all generated files before recompiling.

A mixup can occur where the quartus menu command "project/clean" is an option or even manually delete automatically generated subdirectories.

 

(I had it before that the output of 2 qsys generations with small modifications between 2 versions mixed things up. Cleaning things up got me back on track.)

 

Best Regards,

Johi.

Vicky1
Employee
404 Views

Hi John,

Try to recompile by deleting the 'db' & 'incremental_db' folder from project generated directory.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

Abe
Valued Contributor II
405 Views

Does your project use any DCFIFO IP blocks, If so delete the component, create a new instance and try building it again.

John
Novice
404 Views

Hi Vikas,

Deleting DB & Incremental_db folders did not fix the issue.

 

Thankfully Abe's suggestion of deleting the DC-FIFO component and creating a new one did fix it.

Thanks to everyone for the helpful suggestions.

John.

Reply