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I have a design which is on the limit in terms of FPGA logic utilization. I've noticed that when the fitter fails to find a fit, the "[B] Estimate of ALMs recoverable by dense packing" component of the ALMs needed calculation is 0. When the fitter is able to find a fit, some ALMs are able to be recovered.
+-------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------------------------------------+---------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+---------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device) ; 32,157 / 32,070 ; 100 % ;
; ALMs needed [=A-B+C] ; 32,157 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 30,284 / 32,070 ; 94 % ;
; [a] ALMs used for LUT logic and registers ; 13,292 ; ;
; [b] ALMs used for LUT logic ; 11,471 ; ;
; [c] ALMs used for registers ; 5,521 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 32,070 ; 0 % ;
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 1,873 / 32,070 ; 6 % ;
; [a] Due to location constrained logic ; 0 ; ;
; [b] Due to LAB-wide signal conflicts ; 442 ; ;
; [c] Due to LAB input limits ; 1,431 ; ;
; [d] Due to virtual I/Os ; 0 ; ;
From the fitter report snippet above, I would assume that the 5,521 ALMs used only as registers [A.c] would be candidates for packing with the 11,471 ALMs used only as LUT logic [A.b].
Is there a reason that the fitter fails to pack any ALMs in no-fit cases?
Is there a Quartus option that would force the fitter to attempt to pack ALMs?
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Try a different seeds,
every seeds will have different type of packing and routing,
You can refer to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05172012_146.html for explanation of packing of AL<
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