Wrapper for a module -> any automation?

[ldm_as]

Hi All,

Is there any automation for writing a Verilog wrapper for another Verilog/VHDL module?

Thank you!

[KhaiChein_Y_Intel · Accepted solution]

Hi,

If it is Intel FPGA IP, there is a wrapper auto generated by the software. If it is a user defined module, user have to write their own wrapper file.

Thanks.