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ldm_as
Novice
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Wrapper for a module -> any automation?

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Hi All,

 

Is there any automation for writing a Verilog wrapper for another Verilog/VHDL module?

 

Thank you!

 

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1 Solution
32 Views

Hi,

 

If it is Intel FPGA IP, there is a wrapper auto generated by the software. If it is a user defined module, user have to write their own wrapper file.

 

Thanks.

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1 Reply
33 Views

Hi,

 

If it is Intel FPGA IP, there is a wrapper auto generated by the software. If it is a user defined module, user have to write their own wrapper file.

 

Thanks.

View solution in original post

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