Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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about the error: Error (169079): Pad 51 of non-differential I/O pin 'I2[5]' in pin location N8 is too close to pad 49 of differential I/O pin 'inclk0' in pin location M7 -- pads must be separated by a minimum of 5 pads.


I am pretty short in IOs and no choice about moving IOs to some other locations but the error does not let me to compile the project. How I can work around this problem? is it a real limitation for FPGA? I am using Quartus Prime lite and Quartus 13.1 but both shows the same problem.

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