about vhdl code for cic interpolation filter

[Altera_Forum]

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic interpolation stage for example let differential delay M=1, Interpolation factor R=8,Input bit size be 23 and number of comb sections and integrator sections be N=9.Then how the output bit size change for each comb section.Can anybody explain me with the above mentioned parameters?

[Altera_Forum]

--- Quote Start ---  No, that is my own code for bit growth reposted???  I wanted your code(matlab or rtl) that implements the CIC structure  --- Quote End ---    I came to believe that you haven't done the cic yet but making conclusions directly on bit growth equations.  That is not right. You need to trust the equations.

[Altera_Forum]

--- Quote Start ---  No, that is my own code for bit growth reposted???  I wanted your code(matlab or rtl) that implements the CIC structure  --- Quote End ---    i have done the design in matlab simulink and can i include the entire matlab simulink ?

[Altera_Forum]

--- Quote Start ---  No, that is my own code for bit growth reposted???  I wanted your code(matlab or rtl) that implements the CIC structure  --- Quote End ---    i am attaching the matlab simulink model .Chek the warning messages"overflow occured in sum 2" when you run the model

[Altera_Forum]

--- Quote Start ---  i am attaching the matlab simulink model .Chek the warning messages"overflow occured in sum 2" when you run the model  --- Quote End ---    Well my matlab version is poor man's very old one and failed to open the model. I will try tomorrow at work when my manager is offsite in a meeting.  Or may be FvM got the tools. impasse for me!

[Altera_Forum]

I implemented a CIC interpolator with Quartus CIC compiler and it uses one bit more for each integrator than your design, resulting in equal width of last comb and first integrator (as usually expected) and 49 Bit output width. I must confess that I only CIC implemented decimation filters on my own. Thus I'm not aware of possible errors or ambiguities in Hogenauer's paper related to interpolation filters.

[Altera_Forum]

--- Quote Start ---  Well my matlab version is poor man's very old one and failed to open the model. I will try tomorrow at work when my manager is offsite in a meeting.  Or may be FvM got the tools. impasse for me!  --- Quote End ---    i am using matlab 2008a .What version you are using .If you successful open the model inside the model there is a subsytem after random integer generator.Inside that subsystem there is cic interpolation.But i have tried it with the general model with comb and integrator sections that is mentioned to deeply understand the cic filter working principle about bit growth and i have used convert structure to convert 24 bit to 25 bit and follows.please check it there is overflow in sum 2 that is in the integrator i.e feedback loop second at the rightest end of the subsystem model.

[Altera_Forum]

--- Quote Start ---  I implemented a CIC interpolator with Quartus CIC compiler and it uses one bit more for each integrator than your design, resulting in equal width of last comb and first integrator (as usually expected) and 49 Bit output width. I must confess that I only CIC implemented decimation filters on my own. Thus I'm not aware of possible errors or ambiguities in Hogenauer's paper related to interpolation filters.  --- Quote End ---    Can you please send me the vhdl code that you have done it for cic filter so that i can get clear idea of how to do the coding for cic filter

[Altera_Forum]

--- Quote Start ---  you need sign extend:  data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);  --- Quote End ---    I have not understood clearly what data_24,std_logic_vector(resize(signed(data_23)),24),resize(signed(data_23b)),24) stands for.especially what does signed(data_23b)),24 stands for .can you explain me properly?

[Altera_Forum]

--- Quote Start ---  Can you please send me the vhdl code that you have done it for cic filter so that i can get clear idea of how to do the coding for cic filter  --- Quote End ---   As said, I used the Quartus CIC compiler for the test. There's no readable VHDL code generated, except for the interface component. I have checked the bit widths reported in the parameter list.

[Altera_Forum]

--- Quote Start ---  I have not understood clearly what data_24,std_logic_vector(resize(signed(data_23)),24),resize(signed(data_23b)),24) stands for.especially what does signed(data_23b)),24 stands for .can you explain me properly?  --- Quote End ---    It is an example of adding two 23 bits data(std_logic_vector type) e.g. data_23 and dta_23b such that result data_24 is 24 bits std_logic_vector.  The statement is made up of resize from 23 to 24 (sign extend by one bit) plus cast from signed to std_logic_vector. The signed is needed so that the tool understands how to sign extend.

[Altera_Forum]

--- Quote Start ---  you need sign extend:  data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);  --- Quote End ---    i have tried the above code .Why you are mentioning signed and then std_logic_vector for performing addition.Is data_24 a signed number or unsigned number or you have mentioned it with std_logic_vector?.can you show it with an example in vhdl code?

[Altera_Forum]

--- Quote Start ---  i have tried the above code .Why you are mentioning signed and then std_logic_vector for performing addition.Is data_24 a signed number or unsigned number or you have mentioned it with std_logic_vector?.can you show it with an example in vhdl code?  --- Quote End ---    if your signals are signed you can ignore std_logic_vector and signed expression.  I have assumed your signals are all std_logic_vector and internal computation is signed.  data_24 <= resize(data23,24) + resize(data23b,24);

[Altera_Forum]

--- Quote Start ---  you need sign extend:  data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);  --- Quote End ---    actually i have tried a simple code as you have mentioned above as below  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;  use IEEE.numeric_std.ALL;    ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;  entity project1 is port(a:in STD_LOGIC_vector(23 downto 0);  b:in STD_LOGIC_vector(23 downto 0);  z:out STD_LOGIC_vector(24 downto 0)); end project1;  architecture Behavioral of project1 is  begin    z<=STD_LOGIC_vector (resize(signed(a)),24)+resize(signed(b)),24);    end Behavioral;    and the error i have got is  ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value. ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value. ERROR:HDLParsers:854 - "D:/projects final/signextension/project1.vhd" Line 42. The expression can not be converted to type STD_LOGIC_vector. ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value. ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value. ERROR:HDLParsers:164 - "D:/projects final/signextension/project1.vhd" Line 42. parse error, unexpected CLOSEPAR, expecting SEMICOLON  Process "Check Syntax" failed  What is the problem with my code can you suggest me?

[Altera_Forum]

my bracket syntax error 

 data_24 <= std_logic_vector(resize(signed(data_23),24) + resize(signed(data_23b),24));

[Altera_Forum]

--- Quote Start ---  my bracket syntax error  data_24 <= std_logic_vector(resize(signed(data_23),24) + resize(signed(data_23b),24));  --- Quote End ---    According to the equation given in the cic paper introduction which i have attached previously if for M=1 the output of the first integrator section should be one bit less than the input to the first integrator .As per as my factors of N,M, R that is N=9,M=1,R=8 you got as you have seen so the output of first integrator stage is 32 bits.Now if i have to use the resize function in the integrator stage .I am attaching an integrator circuit and also i am posting my vhdl code that i have written for the integrator stage.Can you tell me the problem in my vhdl code.The input is 33 bit but the output should be 32 bit as per the calculation that you have done in matlab.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity integrator is port( clk:in std_logic; reset:in std_logic; din:in std_logic_vector(32 downto 0); dout:out std_logic_vector(32 downto 0) ); end integrator; architecture Behavioral of integrator is signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0'); begin   process(Clk,reset) begin   if reset='0' then   ifilterout31<="00000000000000000000000000000000"; -- ifilterout32<="000000000000000000000000";   -- dout<="000000000000000000000000";  elsif clk'event and clk='1' then  ifilterout31 <= std_logic_vector(resize((signed(din)+signed(ifilterout31)),31)); -- dout <= ifilterout31; -- ifilterout32 <= ifilterout31;       -- ifilterout32 <= ifilterout31;  end if;  end process ;    end Behavioral; https://www.alteraforum.com/forum/attachment.php?attachmentid=7074

[Altera_Forum]

--- Quote Start ---  my bracket syntax error  data_24 <= std_logic_vector(resize(signed(data_23),24) + resize(signed(data_23b),24));  --- Quote End ---    According to the equation given in the cic paper introduction which i have attached previously if for M=1 the output of the first integrator section should be one bit less than the input to the first integrator .As per as my factors of N,M, R that is N=9,M=1,R=8 you got as you have seen so the output of first integrator stage is 32 bits.Now if i have to use the resize function in the integrator stage .I am attaching an integrator circuit and also i am posting my vhdl code that i have written for the integrator stage.Can you tell me the problem in my vhdl code.The input is 33 bit but the output should be 32 bit as per the calculation that you have done in matlab.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity integrator is port( clk:in std_logic; reset:in std_logic; din:in std_logic_vector(32 downto 0); dout:out std_logic_vector(32 downto 0) ); end integrator; architecture Behavioral of integrator is signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0'); begin  process(Clk,reset) begin   if reset='0' then   ifilterout31<="00000000000000000000000000000000"; -- ifilterout32<="000000000000000000000000";  -- dout<="000000000000000000000000";  elsif clk'event and clk='1' then  ifilterout31 <= std_logic_vector(resize((signed(din)+signed(ifilte rout31)),31)); -- dout <= ifilterout31; -- ifilterout32 <= ifilterout31;    -- ifilterout32 <= ifilterout31;  end if;  end process ;   end Behavioral;

[Altera_Forum]

to add an input of 33 bits in an integrator but output 32 bits follow this code: 

  signal sum : std_logic_vector(32 downto 0) := (others => '0'); process(clk,reset_n) begin if reset_n = '0' then sum <= (others => '0'); elsif clk'event and clk = '1' then sum <= std_logic_vector(signed(din) + signed(sum)); end if; end process ; dout <= sum(31 downto 0);  bit index 31 is assumed dead apparently due to zero insertions so becomes sign bit.

[Altera_Forum]

--- Quote Start ---  to add an input of 33 bits in an integrator but output 32 bits follow this code:   signal sum : std_logic_vector(32 downto 0) := (others => '0'); process(clk,reset_n) begin if reset_n = '0' then sum <= (others => '0'); elsif clk'event and clk = '1' then sum <= std_logic_vector(signed(din) + signed(sum)); end if; end process ; dout <= sum(31 downto 0);  bit index 31 is assumed dead apparently due to zero insertions so becomes sign bit.  --- Quote End ---    Now it is working well now this output of 32 bits will be the input to the next stage and the output for the next integrator will be 34 bits so can you tell me how to add a 32 bit input and the 34 bit feedback signal as shown in the attached file that i have sent it to you.  If it is possible with the resize function can you write the vhdl code for the two stages of integrator section.I have written the code as below  library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity integrator is port( clk:in std_logic; reset:in std_logic; din:in std_logic_vector(32 downto 0) --dout:out std_logic_vector(32 downto 0) ); end integrator; architecture Behavioral of integrator is --signal ifilterout30:std_logic_vector(31 downto 0):=(others =>'0'); signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0'); signal ifilterout32:std_logic_vector(31 downto 0):=(others =>'0'); signal ifilterout34:std_logic_vector(33 downto 0):=(others =>'0'); signal ifilterout33:std_logic_vector(33 downto 0):=(others =>'0');   begin   process(Clk,reset) begin   if reset='0' then   ifilterout31<="000000000000000000000000000000000";  ifilterout33<="0000000000000000000000000000000000";   -- dout<="000000000000000000000000";  elsif clk'event and clk='1' then -- ifilterout30 <= std_logic_vector(resize(signed(din),32));  ifilterout31 <= std_logic_vector(signed(din)+signed(ifilterout31));  ifilterout32 <=ifilterout31(31 downto 0);   ifilterout34 <= std_logic_vector(resize(signed(ifilterout32),34));  ifilterout33 <= std_logic_vector(signed(ifilterout34)+signed(ifilterout33)); -- ifilterout33 <= std_logic_vector(resize(signed( ifilterout32),34)); -- ifilterout32 <= std_logic_vector(resize(signed(ifilterout31),34)); -- dout <= ifilterout31; -- ifilterout32 <= ifilterout31;       -- ifilterout32 <= ifilterout31;  end if;  end process ;    end Behavioral;    please tell what changes to make in the above code so that the output comes.The output is coming as "xxxx.....x" throughout the second integrator stage but as you have told there is no problem in the first integrator stage.

[Altera_Forum]

to add up 32 bits input in an integrator that outputs 34 bits here we go: 

  signal sum : std_logic_vector(33 downto 0) := (others => '0'); process(reset_n,clk) if reset_n = '0' then sum <= (others => '0'); elsif rising_edge(clk) then sum <= std_logic_vector(signed(sum) + resize(signed(din),34)); end if; end process; dout <= sum;

[Altera_Forum]

--- Quote Start ---  to add up 32 bits input in an integrator that outputs 34 bits here we go:   signal sum : std_logic_vector(33 downto 0) := (others => '0'); process(reset_n,clk) if reset_n = '0' then sum <= (others => '0'); elsif rising_edge(clk) then sum <= std_logic_vector(signed(sum) + resize(signed(din),34)); end if; end process; dout <= sum;   --- Quote End ---     The code for the integrator is as below   library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity integrator is port( clk:in std_logic; reset:in std_logic; din:in std_logic_vector(32 downto 0) --dout:out std_logic_vector(32 downto 0) ); end integrator; architecture Behavioral of integrator is --signal ifilterout30:std_logic_vector(31 downto 0):=(others =>'0'); signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0'); signal ifilterout32:std_logic_vector(31 downto 0):=(others =>'0'); --signal ifilterout34:std_logic_vector(33 downto 0):=(others =>'0'); signal ifilterout33:std_logic_vector(33 downto 0):=(others =>'0');   begin   process(Clk,reset) begin   if reset='0' then   ifilterout31<="000000000000000000000000000000000";  ifilterout33<="0000000000000000000000000000000000";   -- dout<="000000000000000000000000";  elsif clk'event and clk='1' then -- ifilterout30 <= std_logic_vector(resize(signed(din),32));  ifilterout31 <= std_logic_vector(signed(din)+signed(ifilterout31));  ifilterout32 <=ifilterout31(31 downto 0);  -- ifilterout34 <= std_logic_vector(resize(signed(ifilterout32),34));  ifilterout33 <= std_logic_vector(resize(signed(ifilterout32),34)+signed(ifilterout33)); -- ifilterout34 <= std_logic_vector(resize(signed(ifilterout33),34)); -- ifilterout33 <= std_logic_vector(resize(signed( ifilterout32),34)); -- ifilterout32 <= std_logic_vector(resize(signed(ifilterout31),34)); -- dout <= ifilterout31; -- ifilterout32 <= ifilterout31;       -- ifilterout32 <= ifilterout31;  end if;  end process ;    end Behavioral;  The final output ifilterout33 is coming as undefined . I tried as you said.But still there is problem in the output.

[Altera_Forum]

--- Quote Start ---  The final output ifilterout33 is coming as undefined . I tried as you said.But still there is problem in the output.  --- Quote End ---   I guess you are talking about functional simulation resuts? The uninitialized register ifilterout32 is propagating to the last integrator stage.  You need to initialize all register variables in functional simulation.