Hi all
I'm running my gate level timing simulation, using sdf file, in design using altmemphy and vendor (Micron) supplied DDR memory model with timing checks. During the "calibration" time of altmemphy, I'm getting lots of setup/hold violations on the DDR interface pins, from FPGA (not DDR chip model).
1. Can someone confirm its ok to have setup/hold violation while calibrating ? I suppose thats what calibration is ;)
2. If so, is there a way to "turn off" these error messages while calibrating, of course, I like to turn it back on in "functional verification" ? I'm using Modelsim and I believe +notimingcheck will turn off the whole simulation ?
3. Or any other clever way to manage these errors ?
Thanks.
