altpll_reconfig and dynamic phase shifting

[Altera_Forum]

I have a need to use both dynamic phase shifting and PLL reconfiguration for a left/right PLL in a Stratix III. I would like to use the ALTPLL_RECONFIG megafunction to handle the reconfiguration part, and my own state machine for the dynamic phase shifting. 

 On the surface this seemed like no problem but there is an issue. The PLL provides a full set of control ports for the reconfiguration and another full set for dynamic phase shifting with one exception: the scanclk input is common. The ALTPLL_RECONFIG megafunction has an output ("pll_scanclk") that must drive the scanclk input, according to the documentation.   I have so far not been able to find sufficient info about the pll_scanclk signal. If it is a pass-through, I can clock my dynamic phase shift state machine from the same clock that is applied to the ALTPLL_RECONFIG clk input. If it is not, but it is at least known to be free-running, I could clock the state machine using the pll_scanclk output signal. Otherwise, I don't see a solution.   Does anyone have any insight or experience with this issue? Thank you!

[Altera_Forum]

It looks like for the altpll_reconfig module, the scanclk out is the same signal as the clk input.  

 I went ahead and built the whole thing and the technology map viewer shows no scanclk output at all. Instead, the signal that drives the clk input also connects to all the places where the RTL code has scanclk going.