Hi,
Say I have two processes looking like this
signal s_valid_reg : std_logic;
signal s_data_reg : std_logic_vector(7 downto 0);
process (CLK, RST)
if (RST = '1') then
s_valid_reg <= '0';
elsif (rising_edge(CLK)) then
s_valid_reg <= VALID;
end if;
end process;
process (CLK,)
if (rising_edge(CLK)) then
s_data_reg <= DATA;
end if;
end process;
I've separated the processes to decrease the global reset fanout.
My question is this:
I've noticed that if I write one process and under the async reset section I reset the data register with 'X' I get the same results, meaning the quartus ignores the async reset signal and does not turn it into an enable signal. Is this behavior mentioned anywhere? Is it vendor dependent?
i.e.
process (CLK, RST)
if (RST = '1') then
s_valid_reg <= '0';
s_data_reg <= 'X';
elsif (rising_edge(CLK)) then
s_valid_reg <= VALID;
s_data_reg <= DATA;
end if;
end process;
