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15311 Discussions

async reset for only some of the registers in a process

yonana
Beginner
178 Views

Hi,

Say I have two processes looking like this

signal s_valid_reg : std_logic;

signal s_data_reg : std_logic_vector(7 downto 0);

process (CLK, RST)

if (RST = '1') then

s_valid_reg <= '0';

elsif (rising_edge(CLK)) then

s_valid_reg <= VALID;

end if;

end process;

process (CLK,)

if (rising_edge(CLK)) then

s_data_reg <= DATA;

end if;

end process;

I've separated the processes to decrease the global reset fanout.

My question is this:

I've noticed that if I write one process and under the async reset section I reset the data register with 'X' I get the same results, meaning the quartus ignores the async reset signal and does not turn it into an enable signal. Is this behavior mentioned anywhere? Is it vendor dependent?

i.e.

process (CLK, RST)

if (RST = '1') then

s_valid_reg <= '0';

s_data_reg <= 'X';

elsif (rising_edge(CLK)) then

s_valid_reg <= VALID;

s_data_reg <= DATA;

end if;

end process;

0 Kudos
2 Replies
SyafieqS
Moderator
137 Views

Hi Yonatan,


You mean in simulation behavior you are seeing same result when data register is resetted with X?

What Quartus are using? Is this occur in latest version too? 


SyafieqS
Moderator
116 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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