Many people told me that FPGA cannot synthesize real numbers but I try real number on Quartus 18.1 Pro on Arria10 and it works. At the same time, i cannot find official document from Intel to clarify this. Any idea if 18.1 can officially synthesize real number? any exception at all?
You may refer to
Verilog HDL Synthesis Support
>Integers and Times are supported. Reals and Realtimes are not supported.
SystemVerilog Synthesis Support
>real and shortreal data types are supported for parameters
VHDL Synthesis Support