can <= concatenate into a big message when use it multiple times?

Altera_Forum · ‎03-16-2013

constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := '5555555555555555';

constant dest_mac_addr : STD_LOGIC_VECTOR (5 DOWNTO 0) := '1078D2AD90CB';

constant src_mac_addr : STD_LOGIC_VECTOR (5 DOWNTO 0) := '001234567890';

constant payload : STD_LOGIC_VECTOR (7 DOWNTO 0) := '0001020304050607';

constant wholepacketlength : STD_LOGIC_VECTOR (1 DOWNTO 0) := '22';

variable tx_data : STD_LOGIC_VECTOR(31 DOWNTO 0);

variable CheckSumResult : STD_LOGIC_VECTOR (31 DOWNTO 0);

variable CheckSumValid : STD_LOGIC;

begin

tx_data <= preamble;

tx_data <= dest_mac_addr;

tx_data <= src_mac_addr;

tx_data <= payload;

H2:crcgen port map(

clk => CLOCK_50, --: IN STD_LOGIC;

data => payload, -- : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datavalid => enableit, --: IN STD_LOGIC;

empty : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

endofpacket : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

checksum => CheckSumResult, --: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

crcvalid => CheckSumValid --: OUT STD_LOGIC

);

tx_data <= CheckSumResult;

Altera_Forum · ‎03-18-2013

Did you try to compile it? If this is part of a process it will fail because you can't instantiate a component inside a process. And even if you could, the multiple tx_data <= *** lines would be ignored and only the last one would be synthesized, giving CheckSumResult.

If it is outside a process then the compile will fail because you are trying to assign multiple values to tx_data.

Altera_Forum · ‎03-18-2013

finally i use a & b to concatenate