can oneapi run on all FPGA boards?

[Ratan]

I currently have a de1-soc but I was unsure if i can use the oneapi base toolkit + Quartus prime + bsp on it to deploy custom logic?

Also do you think it would be possible for me to deploy the hough transform on my de1-soc by using the fpga-selector ? I

I just completed the steps for emulation,optimization and bit stream generation on jupyterlab to get familiar with the development/deployment flow and my next step was to integrate oneapi with a board. What do you suggest I do as my next step?

I have also completed some projects previously using quartus prime, qsys and my de1-soc board. My goal was to try and run these same projects on the same de1-soc or an approved board(as given on the website) but with oneapi this time and code the same script in CPP or DPCPP.

Thank you.

[Ratan]

Also will quartus prime lite edition let me proceed with this plan? or does it have to be the standard or pro edition ?

[hareesh]

Hi,

i working on this issue. let me check and will update you.

Thank you,

[Ratan]

Hello, any updates on this topic?

[hareesh]

Hi,

please go through bellow case. It will help you.

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Trying-to-configure-my-de1-soc-board-with-oneAPI/m-p/1504786

[Ratan]

I might have not explained the whole case clearly,sorry.

So here are my questions , in a simplified manner:

.I was making use of oneapi to deploy the development flow(using quartus prime lite + bsp) onto my de1-soc.

. I was not planning to download the bsp for the de1-soc from an intel source since it is not supported and the bsp simply isnt present for downaload.

.My idea was to use oneapi to generate an RTL file of the hough transform(sycl - on jupyterLabs) and then use that rtl file to generate a custom bsp from quartus prime lite.

. If I am not able to generate an RTL file off oneapi for a provided SYCL script, could I do it for a sample program like vectoradd which is provided from the oneapi-cli menu? or is it not possible to do so at all? Is my plan to use the development flow by generating a custom bsp from quartus prime after generating an RTL file from oneapi not valid at all?

. I would then proceed to  deploy the bitstream onto my de1-soc after the above steps.

Please let me know if my plan to integrate this particular flow is reasonable. If it is, can I please know how to start off with this process? I really have no idea how to start off to convert the SYCL code into a rtl file using oneapi.  Although I am familiar with deploying logic onto the de1-soc after retrieving the .sof file( I have experience working with quartus prime and qsys to deploy logic onto my de1-soc) but my project now ,is to develop and deploy projects onto boards using oneapi instead of qsys and quartus.

[hareesh]

Hi,

ok. just give me some time. I will update to you.

[Ratan]

Hello, any updates on this important topic? 

[hareesh]

Hi,

as of my understanding, you are trying to use oneAPI custom logic in your current project.

• first, you have to build on oneAPI, once it's done just copy the .prj folder into your current Quartus folder, and In platform design time you can use that IP from the IP catalog.

[Ratan]

I don't understand what you mean by 'build on oneAPI'.  Let's say my goal is to work with the Hough Transform prj folder which is on jupyter labs, would I have to make a copy of that file on my linux system and then use oneAPI to generate an rtl file which can then be used on quartus prime to deploy it on my de1-soc board ??

[hareesh]

Hi,

Can we sync up on a call?

please update the available time to arrange a call.

[Ratan]

Yeah sure, can you shoot me an email and I will contact you from that point on wards and we can arrange a time ? 

Thank you so much for your help! 

[hareesh]

ok. i will arrange it. thank you

[hareesh]

Hi,

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/experimental/platform_designer

to use oneAPI C code there is an IP Authoring flow.. which involves compiling oneAPI C code and includes it as part of the component in the platform designer

This is the example design for your requirement, but the problem is it's for the arria10 soc board not for de1.

Unfortunately, it is decided from the strategic level based on the oneAPI roadmap

and cyclone are not part of the support roadmap for now

[hareesh]

Hi,

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/experimental/platform_designer

to use oneAPI C code there is an IP Authoring flow.. which involves compiling oneAPI C code and includes it as part of the component in the platform designer

This is the example design for your requirement, but the problem is it's for the arria10 soc board not for de1.

Unfortunately, it is decided from the strategic level based on the oneAPI roadmap

and cyclone are not part of the support roadmap for now

[hareesh]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.