can you check the error for stopwatch using de2 board

[Altera_Forum]

the error is that after 59min it goes 60 61 62min....... after 99min, it become 00min 00s00 

actually it need to change in hour after 59min i want to show my stopwatch for max 99hr 59min 59s99  this is the stopwatch coding using VHDL  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity stop_watch is  Port ( clk : in STD_LOGIC;  start : in STD_LOGIC;  reset : in STD_LOGIC;  hex0 : out STD_LOGIC_VECTOR (3 downto 0);  hex1 : out STD_LOGIC_VECTOR (3 downto 0);  hex2 : out STD_LOGIC_VECTOR (3 downto 0);  hex3 : out STD_LOGIC_VECTOR (3 downto 0);  hex4 : out STD_LOGIC_VECTOR (3 downto 0);  hex5 : out STD_LOGIC_VECTOR (3 downto 0);  hex6 : out STD_LOGIC_VECTOR (3 downto 0);  hex7 : out STD_LOGIC_VECTOR (3 downto 0)); end stop_watch;  architecture Behavioral of stop_watch is signal count0:std_logic_vector(3 downto 0):=(others=>'0'); signal count1:std_logic_vector(3 downto 0):=(others=>'0'); signal count2:std_logic_vector(3 downto 0):=(others=>'0'); signal count3:std_logic_vector(3 downto 0):=(others=>'0'); signal count4:std_logic_vector(3 downto 0):=(others=>'0'); signal count5:std_logic_vector(3 downto 0):=(others=>'0'); signal count6:std_logic_vector(3 downto 0):=(others=>'0'); signal count7:std_logic_vector(3 downto 0):=(others=>'0'); begin  process(clk,reset) begin  if reset='1' then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=(others=>'0');  count5<=(others=>'0');  count6<=(others=>'0');  count7<=(others=>'0');  elsif rising_edge(clk) then  if start='1' then  if (count7=x"9" and count6=x"9" and count5=x"5" and count4=x"9" and count3=x"5" and count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=(others=>'0');   count5<=(others=>'0');   count6<=(others=>'0');  count7<=(others=>'0');   elsif (count6=x"9" and count5=x"5" and count4=x"9" and count3=x"5" and count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=(others=>'0');   count5<=(others=>'0');   count6<=(others=>'0');  count7<=count7+1;   elsif (count5=x"5" and count4=x"9" and count3=x"5" and count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=(others=>'0');   count5<=(others=>'0');   count6<=count6+1;   elsif (count4=x"9" and count3=x"5" and count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=(others=>'0');   count5<=count5 + 1;   elsif (count3=x"5" and count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=count4 + 1;  elsif (count2=x"9" and count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=count3 + 1;   elsif (count1=x"9" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=count2 + 1;  elsif (count0=x"9") then  count0<=(others=>'0');  count1<=count1 + 1;  else  count0<=count0 + 1;  end if;   end if;   end if; end process;   hex0<=count0; hex1<=count1; hex2<=count2; hex3<=count3; hex4<=count4; hex5<=count5; hex6<=count6; hex7<=count7; end Behavioral;

[Altera_Forum]

you haven't constrained your counters. 

 I will do it as nested ifs starting from count0 towards count7:  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity stop_watch is Port ( clk : in STD_LOGIC; start : in STD_LOGIC; reset : in STD_LOGIC; hex0 : out STD_LOGIC_VECTOR (3 downto 0); hex1 : out STD_LOGIC_VECTOR (3 downto 0); hex2 : out STD_LOGIC_VECTOR (3 downto 0); hex3 : out STD_LOGIC_VECTOR (3 downto 0); hex4 : out STD_LOGIC_VECTOR (3 downto 0); hex5 : out STD_LOGIC_VECTOR (3 downto 0); hex6 : out STD_LOGIC_VECTOR (3 downto 0); hex7 : out STD_LOGIC_VECTOR (3 downto 0) ); end stop_watch; architecture Behavioral of stop_watch is signal count0:std_logic_vector(3 downto 0):=(others=>'0'); signal count1:std_logic_vector(3 downto 0):=(others=>'0'); signal count2:std_logic_vector(3 downto 0):=(others=>'0'); signal count3:std_logic_vector(3 downto 0):=(others=>'0'); signal count4:std_logic_vector(3 downto 0):=(others=>'0'); signal count5:std_logic_vector(3 downto 0):=(others=>'0'); signal count6:std_logic_vector(3 downto 0):=(others=>'0'); signal count7:std_logic_vector(3 downto 0):=(others=>'0'); begin process(clk,reset) begin if reset = '1' then count0 <= (others=>'0'); count1 <= (others=>'0'); count2 <= (others=>'0'); count3 <= (others=>'0'); count4 <= (others=>'0'); count5 <= (others=>'0'); count6 <= (others=>'0'); count7 <= (others=>'0'); elsif rising_edge(clk) then if start='1' then if count0 /= x"9" then count0 <= count0 + 1; else count0 <= x"0"; if count1 /= x"9" then count1 <= count1 + 1; else count1 <= x"0"; if count2 /= x"9" then count2 <= count2 + 1; else count2 <= x"0"; if count3 /= x"5" then count3 <= count3 + 1; else count3 <= x"0"; if count4 /= x"9" then count4 <= count4 + 1; else count4 <= x"0"; if count5 /= x"5" then count5 <= count5 + 1; else count5 <= x"0"; if count6 /= x"9" then count6 <= count6 + 1; else count6 <= x"0"; if count7 /= x"9" then count7 <= count7 + 1; else count7 <= x"0"; end if; end if; end if; end if; end if; end if; end if; end if; end if; end if; end process; hex0 <= count0; hex1 <= count1; hex2 <= count2; hex3 <= count3; hex4 <= count4; hex5 <= count5; hex6 <= count6; hex7 <= count7; end Behavioral;

[Altera_Forum]

Thank sir 

I will test it after I cameback from sch

[Altera_Forum]

hello sir  

for the time set, i need to do with keypad or keyboard. i don't know how to write for this code.

[Altera_Forum]

this is the time to show in LCD. i cannot find the problem. i want to show hour for 01-12. but its also include 00. so after 12hr it become 00hr and then 01 hr. that is the wrong. can u find the error, sir. plz help me. that is very important for me ................. thank sir 

 ------------------------------------------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity counter_up is  Port ( clk : in STD_LOGIC;  SET : in STD_LOGIC;  BTN0 : in STD_LOGIC;  BTN1 : in STD_LOGIC;  BTN2 : in STD_LOGIC;  BTN3 : in STD_LOGIC;  BTN4 : in STD_LOGIC;  BTN5 : in STD_LOGIC;  reset : in STD_LOGIC;  AM : out STD_LOGIC;  hex0 : out STD_LOGIC_VECTOR (3 downto 0);  hex1 : out STD_LOGIC_VECTOR (3 downto 0);  hex2 : out STD_LOGIC_VECTOR (3 downto 0);  hex3 : out STD_LOGIC_VECTOR (3 downto 0);  hex4 : out STD_LOGIC_VECTOR (3 downto 0);  hex5 : out STD_LOGIC_VECTOR (3 downto 0)); end counter_up;  architecture Behavioral of counter_up is signal count0:std_logic_vector(3 downto 0):=(others=>'0'); signal count1:std_logic_vector(3 downto 0):=(others=>'0'); signal count2:std_logic_vector(3 downto 0):=(others=>'0'); signal count3:std_logic_vector(3 downto 0):=(others=>'0'); signal count4:std_logic_vector(3 downto 0):=x"1"; signal reg:std_logic:='0'; begin  process(clk,reset) begin  if reset='1' then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=x"1";  elsif rising_edge(clk) then  if SET='1' then  if (count0=x"9" and BTN0='1') then  count0<=x"0";  elsif (BTN0='1') then  count0<=count0+1;  elsif (count1=x"5" and BTN1='1') then  count1<=x"0";  elsif (BTN1='1') then  count1<=count1+1;  elsif (count2=x"9" and BTN2='1') then  count2<=x"0";  elsif (BTN2='1') then  count2<=count2+1;  elsif (count3=x"5" and BTN3='1') then  count3<=x"0";  elsif (BTN3='1') then  count3<=count3+1;   elsif (count4=x"C" and BTN4='1') then  count4<=x"1";  elsif (BTN4='1') then  count4<=count4+1;   elsif(BTN5='1') then  reg<=not(reg);   end if;   else  if (count4=x"C" and count3=x"5" and count2=x"9" and count1=x"5" and count0=x"9") then  reg<=not(reg);  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<= x"1";   elsif (count3=x"5" and count2=x"9" and count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=count4 + 1;  elsif (count2=x"9" and count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=count3 + 1;   elsif (count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=count2 + 1;  elsif (count0=x"9") then  count0<=(others=>'0');  count1<=count1 + 1;  else  count0<=count0 + 1;  end if;   end if;     end if; end process;   AM <= reg; hex0<=count0; hex1<=count1; hex2<=count2; hex3<=count3; hex4<= count4 when (count4<x"A") else "00"&count4(2 downto 1) when count4=x"C" else "00"&count4(0);  hex5<= "0001" when (count4=x"A" or count4=x"B" or count4=x"C") else "0000"; end Behavioral;