check_timing command (registers with no clock defined)

[Altera_Forum]

Hi guys 

In quartus sdc "check_timing" documentation it says:  "The no_clock check reports whether registers have at least one clock at their clock pin, and that ports determined to be clocks have a clock assigned to them, and also checks that PLLs have a clock assignment."  This is really confuses me.  First of all, if registers don't have a clock, they will be automatically removed in synthesis phase.  consider this case:  module regs_noclock (  input clk,  input data_in,  output data_out );   reg q0,q1; wire genclk  assign genclk = q0; assign data_out = q1;   always @(posedge clk)  q0 =~q0;  always @(posedge genclk)  q1 = data_in;  endmodule  I didn't generate any sdc for this example. the genclk is undefined( or that's what i understood) still when I run the command "check_timing -include {no_clock}" it return 0. so the genclk is know for the tool as a clock.  the question is : in which case timequest reports registers with no clock defined?  Maybe this will give a clear idea: in xilinx, they have the following message: "there are 42 reg/latch with no clock driven by root clock pin" thanks

[Altera_Forum]

that report of no_clock checks (or should check) if there is a latch (no signal connected to clock port of register) or it is connected but without sdc command to define clock. 

 Try "check_timing -include {no_clock}" without s

[Altera_Forum]

Actually it 's "no_clock" . I've rectified the post. And as I said the "no_clock" option returns 0 clocks with issue.  

 The "latches" option checks if there is any latches in the design.

[Altera_Forum]

--- Quote Start ---  Actually it 's "no_clock" . I've rectified the post. And as I said the "no_clock" option returns 0 clocks with issue.   The "latches" option checks if there is any latches in the design.  --- Quote End ---     I think in this scenario the tool inserts default clock(s). But it is hypothetical case as you must have your sdc  The latch option must be overlapping with no_clock

[Altera_Forum]

--- Quote Start ---  I think in this scenario the tool inserts default clock(s). But it is hypothetical case as you must have your sdc  The latch option must be overlapping with no_clock  --- Quote End ---   well, you are right, the command report_sdc shows that timequest has applied a default "create_clock" on clk and the generated clock q0  I couldn't come to have a full understanding of what "no_clock" option do, as I can't imagine an example where this option returns a result different from 0.

[Altera_Forum]

--- Quote Start ---  well, you are right, the command report_sdc shows that timequest has applied a default "create_clock" on clk and the generated clock q0  I couldn't come to have a full understanding of what "no_clock" option do, as I can't imagine an example where this option returns a result different from 0.  --- Quote End ---    No you cannot. This is an example of interaction between two organisations. Synopsis describes their function of "no_clock".  Timequest uses that function but it defaults to the clock it detects and assigns it a period of 1 ns unless it finds a user sdc. But try wiring a register clock port without driving its clock...

[Altera_Forum]

--- Quote Start ---  No you cannot. This is an example of interaction between two organisations. Synopsis describes their function of "no_clock".  Timequest uses that function but it defaults to the clock it detects and assigns it a period of 1 ns unless it finds a user sdc. But try wiring a register clock port without driving its clock...  --- Quote End ---    Hi Kaz  1. I couldn't understand what you mean by "try wiring a register clock port without driving its clock". If the register clock is not driven, this register will be pruned in synthesis, so how can I do that? ( please correct me if I misunderstood something)  2. is there anyway to force timequest to not assign default constraints on the design clocks?. so instead of adding default false constraints, it would be better to report the registers with unconstrained clocks.   thanks kais

[Altera_Forum]

--- Quote Start ---  Hi Kaz  1. I couldn't understand what you mean by "try wiring a register clock port without driving its clock". If the register clock is not driven, this register will be pruned in synthesis, so how can I do that? ( please correct me if I misunderstood something)  2. is there anyway to force timequest to not assign default constraints on the design clocks?. so instead of adding default false constraints, it would be better to report the registers with unconstrained clocks.   thanks kais  --- Quote End ---    I might experiment with tools (in order to understand them) as follows: your register should not be pruned if its output is driving another signal that finally ends up on a pin, assuming compiler doesn't get angry! Or you might locate any default project sdc script somewhere in those corners of the tool to edit it and remove the default clock statement.