Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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clear of IP ALTMULT_ACCUM (MAC)

G_ISAAC
Beginner
1,163 Views

I want to use the MAC IP of the IP catalog of quartus (versions 20.1 and 23.1), when I choose to use the asynchronous clear input in order to have reset on the MAC, my output is in high impedance when the 4th asynchronous clear input option is high or down. 

How can I solve this problem ?

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4 Replies
FvM
Honored Contributor II
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altmult_accum is mapped to dsp hardware on most devices. Which device are you using? There are various clear options? Which are driven by aclr3 in your configuration? Which problem are you exactly facing? Output is tri-state but it shouldn't?
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FvM
Honored Contributor II
1,104 Views

Hi,
an additional question about claimed high impedance output state. How do you determine it and in which configuration?

Output of altmult_accum is a bank of registered LE without a tristate option, there are no internal tristate drivers in FPGA logic. If you instantiate the IP as top level entity, it uses permanently enabled output drivers. I see no way how aclr input could control tristate outputs.

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RichardTanSY_Altera
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As mentioned by FvM, how did you arrive at the high-impedance result?

Could your issue be related to this KDB article?

https://www.intel.com/content/www/us/en/support/programmable/articles/000077849.html


Regards,

Richard Tan


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RichardTanSY_Altera
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know.

Thank you for reaching out to us!

 

Best Regards,

Richard Tan

 

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