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Valued Contributor III
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clocks from PLL to megafunction sdc

Hi! I'm a beginner in learning of constrains.I'm trying to write sdc-file for sdi megafunction. In UG for that megafunction altera offers the following: 

 

derive_clock_uncertainty create_clock -name {rx_sd_refclk_135} -period 7.407 -waveform { 0.000 3.703 } create_clock -name {rx_sd_refclk_337} -period 2.967 -waveform { 0.000 1.484 } create_clock -name {rx_sd_refclk_337_90deg} -period 2.967 -waveform { 0.000 1.484 } create_clock -name {tx_sd_refclk_270} -period 3.703 -waveform { 0.000 1.852 } create_clock -name {tx_pclk} -period 37.037 -waveform { 0.000 18.519 } set_max_delay -from -to 4.430 set_min_delay -from -to 0.000  

 

In my project I have another situation. Clk 270, 135, 337 and 337 with 90 phase I get from PLLs.  

 

So, my question: how to describe clocks from PLLs to megafunction? 

 

I had tried to write sdc in this form:  

 

#******************* # Time Information * #******************* derive_pll_clocks derive_clock_uncertainty set clk_270MHz pll1|altpll_component|auto_generated|pll1|clk set clk_135MHz pll1|altpll_component|auto_generated|pll1|clk set clk_337MHz pll2|altpll_component|auto_generated|pll1|clk set clk_390ph pll2|altpll_component|auto_generated|pll1|clk #*************** # Create Clock * #*************** create_clock -name {clk1} -period 50MHz create_clock -name {clk2} -period 27MHz #************************* # Create Generated Clock * #************************* create_generated_clock -name {c337} -source $clk_337MHz create_generated_clock -name {c135} -source $clk_135MHz create_generated_clock -name {c390} -source $clk_390ph create_generated_clock -name {c270} -source $clk_270MHz #******************** # Set Maximum Delay * #******************** set_max_delay -from -to 4.430 #******************** # Set Minimum Delay * #******************** set_min_delay -from -to 0.000  

 

But quartus sent me warnings 332061 Virtual clock *clk* is never referenced in any input or output dela assigment 

 

Can anyone help me to solve this problem? 

 

May be with example of sdc file with another megafunction, but where clocks are getting from PLL
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Valued Contributor III
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Definitely too much. 

 

create_clock for PLL input clock and derive_pll_clocks will already define all PLL output clocks. 

 

Suggest to review the excellent TimeQuest user guide in Altera Wiki. http://www.alterawiki.com/wiki/timequest_user_guide
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Valued Contributor III
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Your generated clocks don't have any targets or a relationship to the source clock (defaults to -multiply_by 1). That's why you're getting the warning. As mentioned, just use derive_pll_clocks. 

 

derive_pll_clocks and derive_clock_uncertainty should be placed in the file after the create_clock commands. 

 

Also, what are you trying to achieve the the set_max and set_min_delay timing exceptions? If you are trying to represent phase shifts with them, that that is incorrect. Just remove them and use derive_pll_clocks.
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Valued Contributor III
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Thanks for the answers, I'll start reading Rysc user guide!

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Valued Contributor III
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Also check out this online training: 

 

https://www.altera.com/support/training/course/odsw1118.html
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