- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
PLease see the attached files.
I am trying to get some feelings on warnings for combinational loops as latches. The first attached file generates many inferred latches. By adding a clocks, the second attachment generates 512 combinational loops as latches. Any analysis on the situation? And any advice on how to fix the warning while keeping the original functionality?Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It's completely unclear what you are trying to achieve. You are describing asynchronous "memory" by writing data under always @(*). It can be only synthesized as combinational loop with recent Altera FPGA.
There's no significant difference between both examples regarding latch inference.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page