components connection

[MScia1]

Hello everyone,

I am a beginner user of Quartus Prime Lite software (I have to do a project for my University) and I am trying to use the output o a component as the input of the other component... but I cannot do it... I looked for it in the Internet but I do not know whats wrong in my code.

I attach the image of the module I created, the output value "slowclock" or freqDiv32 has to be the input for "updown" in Cont5.

I hope I explained clearly the issue, it is probably a very easy thing but I need some help, please.

Grazie,

Margherita from Italy

[JOHI]

Hello,

Welcome to the forum.

Can you share an archive (use in quartus the option project / archive) with us ?

We might be better able to help you if you do.

Best Regards,

Johi.

[MScia1]

Hello,

sure, I saved the .qar file

I attach it at this answer.

Grazie

[JOHI]

Hello,

FPGA programming is configuring hardware, it is different from microprocessor programming.

Be very carefull with inout ports, if you create a signal in a component, then use out to transfer it to an other component.

Best Regards,

Johi.

[JOHI]

Hello,

I forgot to mention that I added a possible solution to your problem in the previous post.

Best Regards,

Johi.

[SreekumarR_G_Intel]

Hello there ,

In the top module (progetto.vhd), you can use the signal to connect the ports in the component instantiation. Also if you want the port out in the top module ,you can connect the top port to same signal. Then synthesis tool infer the signal using buffer.

I attached modified top module ( progetto.vhd) and synthesized schematic block diagram for your reference.

In case if you dont want to instantiate both the slowdown/updown port , you can comment below two lines in top module.

slowClock <= updown_slowclk_sig;

updown <= updown_slowclk_sig;

Thank you ,

Regards,

Sree

[MScia1]

Hello,

thank you to both of you for your answers!

Now I have undesrtood what you did.

Thank you for the help,

Margherita