Hi,I'm new to testbenches so I set a goal to get those Verilog examples to work under ModelSim. I'm trying to do the simplest of things - to run the counter.v and tcounter.v simulation and create a waveform. However once compiled, I have no objects hence nothing that can be added to the waveform. I get no errors at all, just no objects after I compile. I see the two files under my library, I can click on the testbench file and it opens in SIM but objects window is simply empty. Attempting to add to waveform casues error - no objects found? The funny thing is that if I compile the exact same design and testbench but use the vhdl version examples, then I do have objects available to add to a waveform and all works as expected. What gives? Are the Verilog examples counter.v and tcounter.v screwed? They came from the original distribution and most of all - I get to compile them with no errors? Thanks ~B
It works fine for me. Maybe you want to redo this in a clean directory? or Maybe you could try disable all optimization (e.g. VoptFlow = 0 in modelsim.ini) see if it works? Hope it helps.
yep, when optimization is disabled it worked. Thanks much.But why does this occur? And why doesn't optimization kill the objects if the source is VHDL? It only seems to occur with Verilog source? Thanks ~B