hi together,
i have built a sopc-system with a ddr2 high-performance controller.
when i compile my design i get the following critical warning i do not understand:
Critical Warning: PLL clock inst1|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
what does this warning mean? the clock comes from the input of the nios-system and not from a pll. how can i eleminate this warning?
another critical warning is:
Critical Warning: Source PLL, altpll2:Board_PLL|altpll:altpll_component|altpll2_altpll:auto_generated|pll1, which is feeding the ALTMEMPHY PLL, must have bandwidth mode set to Low instead of Auto
where can i change this setting? its generated automatically so i have not set the bandwidth setting...
it would be nice to get helpful answers!
regards steffen
