Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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dcfifo aclr recovery timming fail

JDrba
Beginner
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Timing analyzer tool report that Recovery timing on reset synchronizer fail. I found I can  apply the following false path assignment on the reset path:

set_false_path -to *dcfifo:dcfifo_component| dcfifo_*:auto_generated|dffpipe_*:wraclr|dffe*a[0] • set_false_path -to *dcfifo:dcfifo_component| dcfifo_*:auto_generated|dffpipe_*:rdaclr|dffe*a[0] 

 

Is it necessary use this to avoid timing violation or is it some another way?

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KhaiChein_Y_Intel
441 Views

Hi,

 

According to the user guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf (Page 19), you have to apply the above two false path assignments on the reset path.

 

Thanks.

Best regards,

KhaiY

 

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KhaiChein_Y_Intel
441 Views

Hi,

 

Do you have any questions?

 

Thanks.

Best regards,

KhaiY

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