It seems ppl use `include to add file that is required to instantiate component in verilog, but when I use `include in my testbench, a warning is issued after successful compile: ** Warning: E:/big_project/tb_fsm_sorter_receiving.v(1): (vlog-2283) Extra semicolon in $unit (global) scope. However if I use include instead of `include then everything work fine.
Why does this happen? Which one should I use in verilog, `include or include ?
Thanks guys!:)
