emif ref clock constraint

[CosmoKramer]

clk_a is available on a pin on the fpga. This is input to EMIF IP as its ref_clk. This also goes to
bunch of other logic on the fabric.

I have a create_clock command for clk_a:

create_clock -name {clk_a} -period 30.0000 -waveform { 0.000 15.0000 } [get_ports {clk_a}]

I got warning that:

Warning(332049): Ignored create_clock at top_projest.sdc(65): Incorrect assignment for clock.
Source node: clk_a already has a clock(s) assigned to it.
Use the -add option to assign multiple clocks to this node.
Clock was not created or updated.

There is no other create_clock command in my sdc file that is related to emif ip.
IP has it is own sdc file, but how does it know about clk_a? will the sdc file have any constraint regarding clk_a?

clk_a is connected to bunch of other logic in the design. I want to add this to asynchronous clock group but i can't as it did not created to begin with.

Please can someone here let me know why I got the error message? Should i use "-add" option to creat clk_a to use it in the asynchronous group?

thank you!

[sstrell]

The clock is connected directly to a PLL by the IP so it knows the clock speed based on the parameter settings in the IP and builds a .sdc based on that.  So you don't need to add an extra constraint for this.

[CosmoKramer]

but clk_a is used elsewhere in the design so I will need to have constraint for it. user_clk_a is also used elsewhere in the design, i will need a constraint for this as well. 

lastly clk_a, user_clk_a should be added to asynchronous group. 

how should i constraint clk_a and user_clk_a ? I am not sure how to create clocks for these to clocks as I do not know how these clocks are named by the tool. 

[AdzimZM_Intel]

Hello,

By right Quartus will auto generate the clock signal name and you don't have to worry about it.

You can verify again in Timing Analyzer for the clock generated by Quartus in TA > Tasks > Clocks > Report Clocks.

If clk_a and usr_clk_a are found out asynchronously, you can straight away set the constraint without creating anymore clock.

Regards,

Adzim

[sstrell]

Just create a clock constraint for user_clk_a as usual.  You can use the Name Finder in the timing analyzer GUI to find the correct target.  Then use create_clock_group as usual.

[CosmoKramer]

I tried to find "emif_usr_clk" port on the emif ip but name finder does not show anything similar to it. And I do not see any generated clocks from ref_clk. 

[AdzimZM_Intel]

Hi,

Does the emif_usr_clk is exported or connect to any other clock input port?

Can you share some snapshot of the SDC File Lists and Clocks from the Timing Analyzer GUI?

Regards,

Adzim

[CosmoKramer]

nope. emif_usr_clk should be generated within the emif ip. I see all the generated clocks from the ip are in the "ignored sdc assignments" list. I have two instances of this ip. Does that cause any issues? it is ignored list because "ip did not find a master clock though it thinks ref_clk as potential master clock". Any reason why tool did not use ref_clk as master clock?

[AdzimZM_Intel]

Hello,

I'm not really sure about that but can you share the design file that I can replicate it at my end?

I can try to check if there is any cause for the EMIF IP to not state the ref_clk as a master clock.

You can send it through Private Message if you're not comfortable to share it in this public forum.

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.