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end of a loop

Altera_Forum
Honored Contributor II
1,141 Views

hi my friends, 

this is my code: 

i want to change the value of "loop_ends" at the end of loopS.but at the end, it never becomes '1' . 

what should i do ? 

 

L1:for s in 0 to NSTAGES-1 generate L2:for t in 0 to 2**s-1 generate begin DUT: entity work.mux port map ( clk => clk, data => n(input_index_end downto input_index_start), input => n(output_index), output => m(output_index) ); end generate; loop_ends<='1' when s=NSTAGES-1 else '0'; end generate;
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Altera_Forum
Honored Contributor II
228 Views

Why would you want this? 

A for-generate expands in place (instantiates a series of components) not in time.
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Altera_Forum
Honored Contributor II
228 Views

 

--- Quote Start ---  

Why would you want this? 

A for-generate expands in place (instantiates a series of components) not in time. 

--- Quote End ---  

 

 

i wanna found when output of loops is prepare, 

when "loop_end" become '1' i found i can use the output!
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Altera_Forum
Honored Contributor II
228 Views

josyb already anwered you. 

VHDL generate loops are NOT sequential instruction loops in the sense of a common software programming language. 

Loops simply instantiate the array of components you specified; this way you don't need to write manually the single stages. 

So the output is immediately ready, apart any delay caused by the actual logic function you implemented.
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Altera_Forum
Honored Contributor II
228 Views

thanks my friends,u r right

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