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error 12006 help

Altera_Forum
Honored Contributor II
1,911 Views

I am getting the error 12006 when i try to compile this code and cant see whats wrong with it can anyone help please? 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

entity mux2_1_struct is 

port ( s,c,p : in std_logic; 

m : out std_logic) ; 

end mux2_1_struct; 

 

 

architecture struct of mux2_1_struct is 

 

 

component and_mux is 

port ( x,y : in std_logic; 

f : out std_logic); 

end component; 

 

component or_mux is 

port (x,y : in std_logic; 

f : out std_logic); 

end component; 

 

component not_mux is 

port( x : in std_logic; 

f : out std_logic); 

end component; 

 

signal n1,n2,n3 : std_logic; 

 

begin 

 

and_mux1 : and_mux port map ( x => c , y => n3 , f => n1); 

 

and_mux2: and_mux port map ( x => s , y => p , f => n2); 

 

not_mux1 : not_mux port map ( x => s , f => n3 ); 

 

or_mux1 : or_mux port map ( x => n1 , y => n2 , f => m);  

 

end struct; 

 

 

 

 

 

 

The error messages im getting are 

Error (12006): Node instance "and_mux2" instantiates undefined entity "and_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
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4 Replies
Altera_Forum
Honored Contributor II
766 Views

Have you added the source code for "and_mux" to the project?

Altera_Forum
Honored Contributor II
766 Views

I dont think so , is the source code for and_mux not in the architecture? or do i have to create it in another file?

Altera_Forum
Honored Contributor II
766 Views

You have a component declaration, but you need an entity and architecture (likely in another file) that define the behaviour.

Ravin
Beginner
39 Views

Hi 

 

I am also getting similar error when i tried to use the UART IP in my project. Kindly suggest some steps to overcome the issue please.

 

Error as folllows

Error (12006): Node instance "comb_3" instantiates undefined entity "Altera_UART_16550". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

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