Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
15774 Discussions

error ID 10170 HDL syntax error while using "typedef enum"

KfirTito
Employee
330 Views

Hi ,

Im using Quartus Prime 19.1.0.670 (Cyclone10LP - 10CL120YF780I7G)

In my module im using "typedef enum ..." to evaluate my state machine current state :

 

//SM to Update SCAN MEM:
typedef
enum logic [3:0] //line(79)
{
SCAN_IF_IDLE = 4'h0,
SCAN_IF_CAPTURE_N = 4'h1,
SCAN_IF_CAPTURE_P = 4'h2,
SCAN_IF_START_N = 4'h3,
SCAN_IF_START_P = 4'h4,
SCAN_IF_EDT_UPDATE_N = 4'h5,
SCAN_IF_EDT_UPDATE_P = 4'h6,
SCAN_IF_CMD_N = 4'h7,
SCAN_IF_CMD_P = 4'h8,
SCAN_IF_SHIFT_N = 4'h9,
SCAN_IF_SHIFT_P = 4'hA,
SCAN_IF_LAST_N = 4'hB,
SCAN_IF_LAST_P = 4'hC,
SCAN_IF_DONE_N = 4'hD,
SCAN_IF_DONE_P = 4'hE
} t_S10_SCAN_IF_STATE; //line(96)

t_S10_SCAN_IF_STATE scan_if_state;

 

 

("scan_if_state" is the case statement in my SM)

 

got the bellow message :

Error (10170): Verilog HDL syntax error at svp_scan_if.sv(79) near text: "logic"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

 

Error (10170): Verilog HDL syntax error at svp_scan_if.sv(96) near text: "}"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

 

Is this Quartus version support this type of writing (sys verilog) ?

 

 

0 Kudos
4 Replies
Nurina
Employee
297 Views

Hi,


I think this syntax is only available in SystemVerilog. Make sure your RTL File is .sv format so you can use this syntax.


Reagrds,

Nurina


Nurina
Employee
297 Views

Sorry I just took a look at the error, seems like your file is .sv.

Let me try this code from my end.



Nurina
Employee
288 Views

Hi,


typedef is supported in this version of Quartus. Can you provide the .qar of this project so I can reproduce the error? Go to Project>Archive Project.


Regards,

Nurina


Nurina
Employee
93 Views

Hi,


We do not receive any response from you on the previous question/reply/answer provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


Reply