error when compiling Arria10 Hard IP for PCIe example design

[巍隗]

My FPGA ：Arria 10 10AT115S2F45E2SG

According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration.

When i compile the example design, i met some errors:

I do not konw how to solve this problem, Please help...

By the way, when i configure the PCIe at Gen2 *8, the compiling of the example design succeed., but error with PCIe Gen3*8.

[AnandRaj_S_Intel]

Hi,

Which version of Quartus is used ?

Attache complete message log?

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

[巍隗]

First，thanks for your attention.

Quartus Version: 18.1 pro(windows 10)

Attachment is the log:

[AnandRaj_S_Intel]

Hi,

we acknowledge the issue​, Will come back on this.

Attached Log.

Best Regards

ARS

(This message was posted on behalf of Intel Corporation)

[JosephC_Intel]

Hi 巍隗,

Just to let you know we've submitted an internal bug for this case. Currently we are waiting for engineering to assign this case.

Will keep you posted if we hear from them.

Thanks,

Joseph

611795

[DNguy4]

is this problem solved? are you able to do the HW test on the design example?

[LSant1]

This issue seems to be about regenerating IP files. Once IP core files are regenerated, compilation should work fine.