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巍隗
Beginner
914 Views

error when compiling Arria10 Hard IP for PCIe example design

My FPGA :Arria 10 10AT115S2F45E2SG

According to the user guide,i have generrated a A10 PCIe example design, the following figure is details about my configuration.

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When i compile the example design, i met some errors:9.png

I do not konw how to solve this problem, Please help...

 

By the way, when i configure the PCIe at Gen2 *8, the compiling of the example design succeed., but error with PCIe Gen3*8.

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6 Replies
AnandRaj_S_Intel
Employee
66 Views

Hi,

 

Which version of Quartus is used ?

Attache complete message log?

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

巍隗
Beginner
66 Views

First,thanks for your attention.

Quartus Version: 18.1 pro(windows 10)

Attachment is the log:

 

AnandRaj_S_Intel
Employee
66 Views

Hi,

 

we acknowledge the issue​, Will come back on this.

Attached Log.

 

Best Regards

ARS

(This message was posted on behalf of Intel Corporation)

JosephC_Intel
Moderator
66 Views

Hi 巍隗,

 

Just to let you know we've submitted an internal bug for this case. Currently we are waiting for engineering to assign this case.

 

Will keep you posted if we hear from them.

 

Thanks,

Joseph

611795

DNguy4
Beginner
66 Views

is this problem solved? are you able to do the HW test on the design example?

LSant1
New Contributor I
66 Views

This issue seems to be about regenerating IP files. Once IP core files are regenerated, compilation should work fine.

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