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I am using SignalTap on a somewhat old FPGA design in a statixgx. This existing design was created using QuartusII 3.0 and I must stick with it because the SERDES has a feature which is no longer supported by altera.
After creating my stp file with the SignalTap editor, I compile successfully and I see a new version of the pof and sof files. I can download the sof file but, when I click the 'Run Analysis' button, I get the following error. Error: Can't run SignalTap II -- download a design with the current SRAM Object File What am I missing?Link Copied
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- The respective SignalTap file must be enabled for the design. This is done automaticly in most cases, but you should check it.
- You may have downloaded a different file, e.g. a same name *.sof from a different directory. - The configuration may have been reset by the on-chip configuration controller, or by an external hardware (e.g. a microprocessor or external configuration controller). On-chip configuration controller can be halted by a tools option. Disabling external controllers may be a problem with designs, that didn't consider debugging requirements.
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