- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

an you give couple example and explain how can you do it

I want to convert 50mhz to 9000hz

Given CLOCK_50 = 50mhz ( in pin planner)

I want to convert by using something like this

Example code:

module Convert(CLOCK_50);

input CLOCK_50;

reg [ ] Q;

reg CLOCK_9000;

always @ (posedge CLOCK_50) begin

//code here convert CLOCK_50 --> CLOCK_9000hz

end

always @(posedge CLOCK_9000hz)

/// i want to this always already 9000hz.

end

Link Copied

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Don't do this in code. Use a PLL instead.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Well, 50MHz is not an integral multiple of 9KHz, so the question is how close do you need to be?

1) You could just divide 50,000,000 Hz by 5,556 and get 8999.28Hz. That is within 0.008%.

2) If you need to get to exactly 9,000Hz, then you need to use a PLL to do a multiply by 9.

So 9*50MHz is 450MHz, divided by 50,000 is exactly 9,000Hz.

Depends on your exact requirement.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

maybe we have wrong idea.

my idea is i want to understand the code in the always @ (posedge CLOCK_50) begin.

For example i wrote this code

module Convert(CLOCK_50);

input CLOCK_50;

reg [ 25: 0 ] Q;

reg CLOCK = 0;

always @ (posedge CLOCK_50) begin

if (Q == 25000000 ) begin

Q <= 0;

CLOCK = !CLOCK ;

end

else

Q <= QQ + 1;

end

So i have reg [25:0] Q. is this Q is 25 bit???

if(Q==25000000) // is if Q == 25bit then the CLOCK = 1 hz? or 1mhz ? i dont know .

This main question i have to understand in this alway @(posedge clock_50) begin clock_50 = 50mhz.

i want to understand how the code work in here. if i want to get 50000000/9000 = 5555.5 or 5556

so if i want to get 9000 then i ran

If(Q==5556)

Q<=0

CLOCK <=1; // this is now clock == 9000hz?

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

First a **reg [25:0]** value is a 26 bit binary number, and can have a value between 0 and 2^26-1, or 67,108,863.

**@(posedge clock_50)** is going to toggle every 20ns (assuming a 50MHz clock input). So each count will be 20ns.

5556 * 20ns will be 111.12usec, or 8999.28 KHz.

Do you have access to a graphical verilog simulator as part of your Quartus install? That may make it easier for you to understand.

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hello,

Does the above reply answer your question?

Regards,

Nurina

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content

Hello,

We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

P/S: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey

Regards,

Nurina

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page