hi all,
i'm trying to compile a project for the arria 10 development board using Quartus 18.
the synthesis passes but the fitter fails with the following message:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 OCT logic block(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 OCT logic block, which is within Generic Component emif_hps.
Info(14596): Information about the failing component(s):
Info(175028): The OCT logic block name(s): hps_qsys_0|emif_hps|altera_emif_a10_hps_inst|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst~_Duplicate_3
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: S2P_SERDATA of 0 (1 location affected)
Info(175029): TERMINATIONLOGIC_X78_Y169_N11. Already placed at this location: OCT logic block hps_qsys_0|emif_hps|altera_emif_a10_hps_inst|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst~_Duplicate_2
what is the issue here?
thanks
