gated and muxed clocks with classic timing analyzer

[Altera_Forum]

For diagnostic purposes we have added gated and muxed clocks to our fpga design. 

 The gated clock is the inverse of the input clock.   The muxed clock logic switches the output clock to the input clock for loopback mode.  Classic timing analyzer gives all kinds of warnings about ripple/gated clocks and the timing fails 1000's of paths. The timing passes when we take out the gated/muxed clocks.  We use the Cyclone device. This is added logic to an already completed/released design. We use Verilog and the logic is  assign clock_in_loopback = fpga_loopback ? clock_out : clock_in;  assign clk_in_inverse = inv_clk_en ? ~clk_in : clk_in;  How de we constrain these clocks in classic timing analyzer to make the timing pass? Can we do the logic another way that would be better?  Thanks

[Altera_Forum]

Since you're doing it with gates, it gets more complicated, because you are introducing clock skew. I assume when you switch what drives the clock, you don't care what happens? For example, if you drive out clk_in, and less than a half cycle later you drive out ~clk_in, then you would have a transfer from clk_in to ~clk_in, which means you're requirement is half the period of clk_in.  

 You can put an absolute clock on the ouput of the mux. That works nicely as it ignores all the logic leading up to the that point, so there is no gating, not multiple clocks, etc. But it's bad in that it ignores this extra delay, so interfaces to other domains(or I/O) won't account for this extra delay.  You may want to assign inv_clk_en with the Not a Clock assignment, so it gets ignored.  Just some ideas to get you started. TimeQuest is generally much better equipped for this, although it is generally doable with the Classic Timing Analyzer.

[Altera_Forum]

--- Quote Start ---  You may want to assign inv_clk_en with the Not a Clock assignment, so it gets ignored.  --- Quote End ---    That assignment works only if inv_clk_en is an input pin. The last time I looked at that assignment, it was not available for internal signals.  Always be careful when driving clocks with internal logic even if there are no reported timing violations. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754.

[Altera_Forum]

True. I seem to remember applying a clock constraint to a register, and then apply Not a Clock to it to get it to work. (No guarantees). You could probably just cut timing from inv_clk_en. The net affect is you want the output to be analyzed with the main clock domain frequency(setup of the clock period, hold requirement of 0ns) whether its inverted or not.