I created a base clock coming from a top-level port in the design. The problem I'm having is when I try to get the source clock pin using 'get_clock_info -master_clock_pin my_clk' it returns nothing. If I do that with a generated clock it works though.
tcl> create_clock -name "my_clk" -period 8 [get_ports clk]
tcl> create_generated_clock -name "my_clk_div2" -divide_by 2 -multiply_by 1 -source [get_ports clk] -master_clock clk_eri_sys______a_125_000k_c_p [get_nets clk_div2]
tcl> get_clock_info -master_clock_pin my_clk
tcl> get_clock_info -master_clock_pin my_clk_div2
Is there any step that I'm missing?
With Vivado it's a bit clunky, but it works like this and it would return either a port or a pin name
tcl> get_property SOURCE_PINS [get_clocks <CLOCK_NAME>]
A base clock would not have a master_clock_pin. With a generated clock, you can use the -master_clock option to select a source clock if there are multiple clocks at the source.
In your create_generated_clock command, you don't even need the -master_clock option since there's only one clock at the source.
If that's the case, is there any other command I could use to get the source pin/port of a base clock (or any clock)? My intent is to have an automated script that generates new clocks like this. In this case 'get_clock_source_pins' is just a dummy placeholder function.
tcl> create_generated_clock -source [get_clock_source_pins my_clk] -name ...
Not that I know of. If you've created a clock with create_clock, you targeted it to an I/O port (get_ports) so that would be the source for any generated clock you create (unless you create generated clocks based on other generated clocks).
If we're talking about PLLs, you can simply use derive_pll_clocks instead.