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14949 Discussions

get register driven clock name

EBoln
New Contributor I
1,020 Views

How to get clock name on which the register is running in Q std?solved only using get_path, but during synthesis I get an error because get_path is not from sdc or sdc_ext package

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1 Solution
25 Replies
KennyT_Intel
Moderator
786 Views

where do you plan to put this get_register? Are you planning to put it in *.sdc? If yes, you may have to run timing analyzer to get the correct nodes.




EBoln
New Contributor I
771 Views
 
I am describing a module in which there are several clock signals, and several instances of this module are planned, operating at different frequencies. I am going to make a qip file with source code and SDS file, in which I want to describe data for correct time analysis. I would also like this description to be correctly taken into account by fitter
KennyT_Intel
Moderator
731 Views

To find the correct nodes, what you can do is go to Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes that you want.


EBoln
New Contributor I
723 Views

EBoln_0-1603685628851.png

set_clock_groups -physically_exclusive -group [get_clocks {clk}] -group [get_clocks {vidi_clock}]

however, in the toplevel file, these clocks are named differently. And I would like to use this module in other projects. That is, create an IP core and just use

sstrell
Honored Contributor III
715 Views

If you want to name the clocks differently for timing analysis, in your clock constraints (create_clock or create_generated_clock), use the -name option.  This won't change their names in the design, however.

EBoln
New Contributor I
701 Views

What if I don't have access to the main design?

KennyT_Intel
Moderator
636 Views

It will be still the same, have to try to look for nodes by:

Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes


KennyT_Intel
Moderator
564 Views

any further queries?


EBoln
New Contributor I
560 Views

Yes, how does set_multicycle_path help me do my path analysis correctly?

sstrell
Honored Contributor III
545 Views

I think multicycle is just being given as an example of accessing one of the GUI dialog boxes to access the Name Finder tool.  There's no way to search for nodes in the timing netlist without going through one of these dialog boxes and I guess multicycle was selected just as an example.  You don't need multicycle for the design.

EBoln
New Contributor I
538 Views

even worse, I don't need a graphical interface. i want to describe in sdc

sstrell
Honored Contributor III
535 Views

True, but the GUI dialog boxes make it easy to form SDC constraints with correct syntax and they're the only way to get to the Name Finder.

EBoln
New Contributor I
531 Views

that is, there is no analog of entity-bound SDC files for quartus std?

KennyT_Intel
Moderator
453 Views

Can you describe more on the previous question?

Once you set multicylce, you should be able to open up timing analyzer to analyze for that path.


KennyT_Intel
Moderator
431 Views

any update?


EBoln
New Contributor I
428 Views

Ok, how to describe this multiplexer correctly? But "my module" must be used in different projects, and i don't know whats clocks used on "Tol level"

KennyT_Intel
Moderator
408 Views

Usually, Multiplexer does not consist of a clock. Does your Mux have a clock? If no, you do not need to set any clock for it. Timing analyzer analyze the path from register to register, once you have a register, you should have a clock to be constraint.


EBoln
New Contributor I
405 Views

My multiplexer switches the clock. And to describe it, you need to describe the clock groups

KennyT_Intel
Moderator
402 Views
EBoln
New Contributor I
365 Views

yes, but clkA and clkB on Top, to which I have no access and I do not know anything about it

EBoln_0-1606725805892.png

 

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