get register driven clock name

[EBoln]

How to get clock name on which the register is running in Q std?solved only using get_path, but during synthesis I get an error because get_path is not from sdc or sdc_ext package

[Kenny_Tan]

where do you plan to put this get_register? Are you planning to put it in *.sdc? If yes, you may have to run timing analyzer to get the correct nodes.

[EBoln]

I am describing a module in which there are several clock signals, and several instances of this module are planned, operating at different frequencies. I am going to make a qip file with source code and SDS file, in which I want to describe data for correct time analysis. I would also like this description to be correctly taken into account by fitter

[Kenny_Tan]

To find the correct nodes, what you can do is go to Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes that you want.

[EBoln]

set_clock_groups -physically_exclusive -group [get_clocks {clk}] -group [get_clocks {vidi_clock}]

however, in the toplevel file, these clocks are named differently. And I would like to use this module in other projects. That is, create an IP core and just use

[sstrell]

If you want to name the clocks differently for timing analysis, in your clock constraints (create_clock or create_generated_clock), use the -name option.  This won't change their names in the design, however.

[EBoln]

What if I don't have access to the main design?

[Kenny_Tan]

It will be still the same, have to try to look for nodes by:

Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes

[Kenny_Tan]

any further queries?

[EBoln]

Yes, how does set_multicycle_path help me do my path analysis correctly?

[sstrell]

I think multicycle is just being given as an example of accessing one of the GUI dialog boxes to access the Name Finder tool.  There's no way to search for nodes in the timing netlist without going through one of these dialog boxes and I guess multicycle was selected just as an example.  You don't need multicycle for the design.

[EBoln]

even worse, I don't need a graphical interface. i want to describe in sdc

[sstrell]

True, but the GUI dialog boxes make it easy to form SDC constraints with correct syntax and they're the only way to get to the Name Finder.

[EBoln]

that is, there is no analog of entity-bound SDC files for quartus std?

[Kenny_Tan]

Can you describe more on the previous question?

Once you set multicylce, you should be able to open up timing analyzer to analyze for that path.

[Kenny_Tan]

any update?

[EBoln]

Ok, how to describe this multiplexer correctly? But "my module" must be used in different projects, and i don't know whats clocks used on "Tol level"

[Kenny_Tan]

Usually, Multiplexer does not consist of a clock. Does your Mux have a clock? If no, you do not need to set any clock for it. Timing analyzer analyze the path from register to register, once you have a register, you should have a clock to be constraint.

[EBoln]

My multiplexer switches the clock. And to describe it, you need to describe the clock groups

[Kenny_Tan]

Is this the multiplexer that you are working at?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/exm-tq-clock-mux.html

[EBoln]

yes, but clkA and clkB on Top, to which I have no access and I do not know anything about it