Hi I'm new here.I've recently bought a cheap cyclone 2 dev board, EP2C5T144 with the soul intent can I produce a picture via HDMI (DVI) expressed from the IO pins of the fpga directly, looking around I found some nice information from fpga4fun, however some of the code is for xilinx based chips such as the dcm. Long story short I've set her up and getting no output, I wonder what gives? I've added a ALT_PLL, started with 50mhz in and output 25mhz and 250mhz clocks , after which followed the brief explanation of hdmi on a fpga at fpga4fun as best I can, the only thing cyclone 2 didn't support but cyclone 3 does support is the alt_buf's so I used assigns and directly apply the changes that way to the output tmds[x] p/n and pixelclock. Still nothing. pulled my hair out for a few days over this, I wonder if anyone else has been successful. One guy has ... https://github.com/charcole/neogeohdmi the question is why doesn't his code work for me (stripped it down to the parts I require) if anyone has a similar setup or the same board, could they walk me through what I'm meant to do exactly, I've followed the pin sheet on his wires.md specifically to the hdmi cable and breakout board options I have and no signal, the only thing that gets a result is the 5v line but that's it 'hdmi is available' no signal. Writing this project in verilog and would appreciate some help. To start with a low compatible resolution and test pattern would be sufficient first step. Chris
--- Quote Start --- I assume it does, but just to be sure does it work in simulation? --- Quote End --- Ive been unable to manage to get the simulation working as I'm still getting use to the interface I'm assuming by what you're saying I will be able to see the pll clocks and the data flow of the tmds encoder red green blue outputs and assigns , I'll try to install altera sim executable as that may be why . Ive got one more thing to try and that's the h sync and v sync may be wrong or incompatible to my tv units . chris Edit: Got the altera modelsim working now, i see data on the output lines... strange, feels like a hardware issue or something wrong with my wiring perhaps? Or tv incompatability, although I have two branded tv's I'm testing it on right now, hmm... screenshot: https://i.imgur.com/oft0yuo.png
You mention generating a 250MHz clock from you PLL. Running much, or possibly anything, on Cyclone II at that speed is likely to be tricky.How much logic do you run at this speed? Have you added timing constraints to your design? Does it meet them? The Neo Geo MVS project you refer to doesn't appear to be running anything at that speed... Cheers, Alex
Well I was able to use PLL to get 250mhz, but regardless even at 125Mhz for the tmds and 25Mhz for the pixelclock I'm seeing nothing based on his code.Hmmm need a scope to even confirm there's data flowing out of the pins, but simulator shows theres data, tv says no signal. You have any idea what I should do from now?
Hi Solidcore,1. Check the properties of the monitor and adjust the properties of the monitor as per code or modify the code (Resolution,Vsync,Hsync). 2. Check the monitor is using interlace or progressive scanning. 3. Check the Timing Vsync, Hsync, Pexel clock & porch. 4. Only write a code for solid pattern i.e white/black. Without proper sync signals monitor will not display and it will go to sleep mode. For sample full projects at terasic website. https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=68&no=582&partno=3 Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Update: I have succesfuly got the hdmi output through from cyclone 2 fpga to the phillips monitor via hdmi, it turnd out that I had my clock and a color line mixed up in my wiring, head banging over :) my samsung wont work yet but we'll see what code can achieve.Edit: Samsung now works, but the Hdmi/dvi port cuts out , probably sync issue and different settings required Will investigate. Edit: it appears that the cyclone II fpga is limited to 480p , 720p is a difficult thing to achieve at the maximum mbps of the cyclone II, any ideas? I've tried caskading two ppl's with their output and input clocks to trick into higher mhz (that works fine) but beyond that the output doesn't support 640mbps on lvds via differential pairs TX out.
Regarding PLL, I believe Cyclone II doesn't allow PLL cascading, although it appears you can simply take the PLL# 1 clock via 'PLL output' and then physically pass it over to the 'PLL input' which another PLL# 2 can use as a clock input, effectively cascading PLL's. Is there any real world side effect for this and does the length of the wire matter? In cyclone III it appears you can cascade PLL's Nice! ... shame about II but I guess inside it does not have a physical pathway or can global clock be used in that respect ?Also does anyone know how to succesfully get the clocks for 720p out of a cyclone II , even overclocking PLL inputs by tricking PLL# 2 to believing PPL# 1 is giving it say 50mhz when in reality it's giving it 100mhz ?