help creating delay in fsm

Altera_Forum · ‎11-26-2013

can someone help me, having trouble on creating delay for each state in this moore model....

exmple state0 delay for 30 sec state 1 dealy for 10 sec and etc....

`timescale 1s/1smodule fsm( clk, rst, inp,m, outp);
   input clk, rst, inp,m;
   output outp;
parameter state0=3'b000;
   reg  state;
   reg outp;
   integer i;
   always @( posedge clk, posedge rst )
   begin
   if( rst )
       state <= state0;
   else
   begin
       case( state )
       3'b000:
       begin
            if( inp ) state <= 3'b001;
            else state <=3'b000;
       end
       3'b001:
       begin
            if( inp ) state <= 3'b010;
            else state <= 3'b001;
       end
       3'b010:
       begin
            if( inp ) state <= 3'b011;
            else state <= 3'b010;
       end
       3'b011:
       begin
            if( inp ) state <= 3'b100;
            else state <= 3'b011;
        end      
       3'b100:
       begin
            if( inp ) state <= 3'b101;
            else state <= 3'b100;end
       3'b101:
       begin
            if( inp ) state <= 3'b110;
            else state <= 3'b101;end
       3'b110:
       begin
            if( inp ) state <= 3'b111;
            else state <= 3'b110;
       end
        3'b111:
       begin
            if( inp ) state <= 3'b000;
            else state <=3'b111;
       end
       endcase
   end
end
always @(posedge clk, posedge rst)
begin
       if( rst )
       outp <= 0;
     else if (m==0)
       begin
         
       if(state == 3'b000)
       outp <= 3'b000;
       else if(state == 3'b001)
       outp <= 3'b001;
       else if(state == 3'b010)
       outp <=  3'b010;
       else if(state == 3'b011) 
       outp <= 3'b011;
       else if(state == 3'b100) 
       outp <= 3'b100;
       else if(state == 3'b101)
       outp <= 3'b101;
       else if(state == 3'b110) 
       outp <= 3'b110;
       else if(state == 3'b111)
       outp <=3'b111;
       else outp <= 0;
       end
    else if (m==1)
       begin
       if(state == 3'b000)
       outp <=#30 3'b000;
       else if(state == 3'b001)
       outp <= 3'b001;
       else if(state == 3'b010)
       outp <=  3'b011;
       else if(state == 3'b011)
       outp <= 3'b010;
       else if(state == 3'b100)
       outp <= 3'b110;
       else if(state == 3'b101)
       outp <= 3'b111;
       else if(state == 3'b110) 
       outp <= 3'b101;
       else if(state == 3'b111)
       outp <=3'b100;
       else outp <= 0;
       end
    else outp <= 0;
end
  
  
endmodule
test bench

module fsm_test;
reg  clk, rst, inp,m;
wire outp;
integer i;
fsm dut( clk, rst, inp,m, outp);
initial
begin
   clk<= 0;
   rst <= 1;
   i<=1;inp<=1;
  # 5 rst <= 0;
   m<=0;#200 m<=0;#70;
 end
      
always# 10 clk=~clk;
endmodule