Warning: Command has been deprecated. Please use -board=<value> instead of --board <value>
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Linking Object files....
aoc: Optimizing and doing static analysis of code...
aoc: First stage compilation completed successfully.
Compiling for FPGA. This process may take a long time, please be patient.
Error (170143): Final fitting attempt was unsuccessful
Error: An error occurred during routing
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 452 warnings
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 2295 warnings
Error (23035): Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error (23031): Evaluation of Tcl script s10_partial_reconfig/flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 9 errors, 2295 warnings
Error (16546): Cannot load final database - ensure all earlier stages of the compiler have completed.
Error (17941): The design could not be loaded due to errors.
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script scripts/adjust_plls_mcp.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 4 errors, 0 warnings
Error: Compiler Error, not able to generate hardware
Below is a similar previous case about Error (170143) for your reference.
May be you have to reduce some code in your kernel in order to solve the congestion issue.
In the report only DSP usage is above 25%, so the routing problem should due to DSP.
Does that mean we can never make full use of DSP?
What percentage of DSP is a reasonable design that can be routed?
Thank you very much
Regarding that particular DSP usage question you mentioned above, perhaps you can open a new thread in Intel® High Level Design forum for better confirmation. The link of the forum is provided below.