Hi All,
I am new to Verilog, and am hoping someone may have some suggestions how to make the output from this code smaller.
Lots of detail associated with the module has been removed until I end up with a small sample that appears to compile to quite a large chunk of LEs (about 100).
This seems a huge amount of real-estate given the simplicity of the state machine etc.
Any thoughts appreciated.
Thanks,
Mark
================
module needs_optimization
(
input clk,
input [17:0]data,
input start,
output reg [7:0]d_out,
output reg busy
);
reg [4:0] state;
reg [17:0] input_data;
reg [7:0] output_LSB;
always @(posedge clk)
begin
if(start)
begin
state <= 0;
d_out <= 0;
input_data <= data;
end
else if(state < 14)
begin
if(input_data[16]) // MSB processing stripped
state <= 14;
else
state <= state+1;
end
else if(state == 14)
begin
state <= 15;
output_LSB <= 11; // LSB processing stripped (output_LSB can be 0..11)
end
else if(state == 15)
begin
state <= 16;
d_out <= d_out + output_LSB;
end
else if(state == 16)
begin
state <= 17;
d_out <= (d_out << 1);
end
end
endmodule
