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library ieee;

use ieee.std_logic_1164.all;

entity eight_1 is

port(a:in std_logic_vector(7 downto 0); s: in std_logic_vector(2 downto 0); y: out

std_logic);

end eight_1;

architecture d_f of eight_1 is

begin

process(a,s)

begin

if s = "000" then y (0) <=a;

elsif s = "001" then y (1) <=a;

elsif s = "010" then y (2) <=a;

elsif s = "011" then y (3) <=a;

elsif s = "100" then y (4) <=a;

elsif s = "101" then y (5) <=a;

elsif s = "110" then y (6) <=a;

else y (7) <=a;

end if;

end process;

end d_f;

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Hi,

Replace all IF statement like **if s = "000" then y (0) <=a; **with** if s = "000" then y <= a(7); **since y is a one bit output.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

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