Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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how can i eliminate this ----> Error (10482): VHDL error at Controller.vhd(17): object "UNSIGNED" is used but not declared

zch
Beginner
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a_x_h_75
New Contributor III
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The clue is in the error - declare it - either as a signal or a variable within the process...

 

Unless you're using numeric_std package. In which case this becomes a defined type. So you'll need to change the name of your signal.

 

Cheers,

Alex

 

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