Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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how can simulate the project contains a .qxp file by modelsim-altera???help!!

Altera_Forum
Honored Contributor II
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as the title. 

I want to simulate the project which contains a .qxp file, I do it as follows: 

 

1. New project 1 , named counter_ip, synthesis , and then Project-export design partition, so get the .qxp file; 

2. New project 2, named top_prj, add the .qxp file generated by step 1 to project2, and instance it ; synthesis; 

3. new testbench, and call the modelsim-altera for simulation; 

4. got errors in modelsim-altera like this :  

Error: (vsim-3033) C:/Users/Vinter/Desktop/Project_out/top_prj/top_prj.v(18): Instantiation of 'counter_ip' failed. The design unit was not found. 

 

 

 

thanks very much!!!
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Altera_Forum
Honored Contributor II
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anyone?? anyone??

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Altera_Forum
Honored Contributor II
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add : 

 

when i select gate_level simulation; 

quartus send the message : can not find the top_prj.sft,run the EDA netlist writer! 

 

what does it mean by this???
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Altera_Forum
Honored Contributor II
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Now I can simulate the .qxp by gate_level simulation ,but not rtl or post_routing simulation. 

 

how can .qxp be simulated in rtl or post route way? thanks
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Altera_Forum
Honored Contributor II
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You can run Netlist simulation for design having .qxp files (As you have already done Gate Level Simulation) 

or  

Alternatively for RTL simulation add your HDL files (.v, .vhd, .sv) to simulation script.  

qxp is not recognizable by Modelsim simulator. 

 

hope this answers your question. 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
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Altera_Forum
Honored Contributor II
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thanks. 

another question: 

what is the difference between rgate_level and post_routing simulation?  

thanks!
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Altera_Forum
Honored Contributor II
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Gate Level simulation (Netlist simulation) with Quartus there are two level where you can do Netlist simulation 

- Post Synthesis (Synthesized netlist) 

- Post Fit (Post Place and route netlist) 

 

 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
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Altera_Forum
Honored Contributor II
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thanks so much!

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