how to compile 3 vhdl program to make 1 project and compile it into flex10k up2 board

[Altera_Forum]

hi, i have 3 vhdl file..its all my project file..how do i compile it and load it into the board because when i compile it showing top level entity undefined..im using quartus II 8.1..help me pleasee..

[Altera_Forum]

You need to write top level file, where you instantiate your project files.

[Altera_Forum]

how to write it, can you show me pleasee..?i'm really desperate right now coz i have to submit my project tomorrow...

[Altera_Forum]

Here is nice example from Altera: http://www.altera.com/support/examples/vhdl/v_hier.html 

 Basically you need to connect your modules together in that vhdl top level file.

[Altera_Forum]

thanks...but i don't know to connect the module together..can you show me pleasee..

[Altera_Forum]

I don't know what else you need, the link on Altera's website is the simplest way to explain how to regroup several components in a top level file.

[Altera_Forum]

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